eb76bc38ff
If the AVL in a VSETVLIInfo is the output VL of a vsetvli with the same VLMAX, we treat it as the AVL of said vsetvli. This allows us to remove a true dependency as well as treating VSETVLIInfos as equal in more places and avoid toggles. We do this in two places, needVSETVLI and computeInfoForInstr. However we don't do this in computeInfoForInstr's vsetvli equivalent, getInfoForVSETVLI. We also have a restriction only in computeInfoForInstr that the AVL can't be a register as we want to avoid extending live ranges. This patch does two interlinked things: 1) It adds this AVL "peeking" to getInfoForVSETVLI 2) It relaxes the constraint that the AVL can't be a register in computeInfoForInstr, since it removes a use of the output VL which can actually reduce register pressure. E.g. see the diff in @vector_init_vsetvli_N and @test6 Now that getInfoForVSETVLI and computeInfoForInstr are consistent, we can remove the check in needVSETVLI. We also need to update how we update LiveIntervals in insertVSETVLI, as we can now end up needing to extend the LiveRange of the AVL across blocks.
77 lines
3.0 KiB
LLVM
77 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O3 -mattr=+v -lsr-drop-solution | FileCheck --check-prefix=CHECK %s
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64-unknown-linux-gnu"
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define ptr @foo(ptr %a0, ptr %a1, i64 %a2) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a4, a2, e8, m8, ta, ma
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; CHECK-NEXT: bne a4, a2, .LBB0_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a1)
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_2: # %if.then
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; CHECK-NEXT: add a2, a0, a2
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; CHECK-NEXT: sub a5, a2, a4
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; CHECK-NEXT: mv a3, a0
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; CHECK-NEXT: .LBB0_3: # %do.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vle8.v v8, (a1)
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; CHECK-NEXT: vse8.v v8, (a3)
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; CHECK-NEXT: add a3, a3, a4
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; CHECK-NEXT: add a1, a1, a4
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; CHECK-NEXT: bltu a3, a5, .LBB0_3
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; CHECK-NEXT: # %bb.4: # %do.end
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; CHECK-NEXT: sub a2, a2, a3
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; CHECK-NEXT: vsetvli a2, a2, e8, m8, ta, ma
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; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a1)
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; CHECK-NEXT: vse8.v v8, (a3)
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; CHECK-NEXT: ret
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entry:
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%0 = ptrtoint ptr %a0 to i64
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%1 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %a2, i64 0, i64 3)
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%cmp.not = icmp eq i64 %1, %a2
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br i1 %cmp.not, label %if.end, label %if.then
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if.then: ; preds = %entry
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%add = add i64 %0, %a2
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%sub = sub i64 %add, %1
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br label %do.body
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do.body: ; preds = %do.body, %if.then
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%a3.0 = phi i64 [ %0, %if.then ], [ %add1, %do.body ]
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%a1.addr.0 = phi ptr [ %a1, %if.then ], [ %add.ptr, %do.body ]
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%2 = tail call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.i64(<vscale x 64 x i8> undef, ptr %a1.addr.0, i64 %1)
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%3 = inttoptr i64 %a3.0 to ptr
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tail call void @llvm.riscv.vse.nxv64i8.i64(<vscale x 64 x i8> %2, ptr %3, i64 %1)
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%add1 = add i64 %a3.0, %1
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%add.ptr = getelementptr i8, ptr %a1.addr.0, i64 %1
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%cmp2 = icmp ugt i64 %sub, %add1
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br i1 %cmp2, label %do.body, label %do.end
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do.end: ; preds = %do.body
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%sub4 = sub i64 %add, %add1
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%4 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %sub4, i64 0, i64 3)
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br label %if.end
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if.end: ; preds = %do.end, %entry
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%a3.1 = phi i64 [ %add1, %do.end ], [ %0, %entry ]
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%t0.0 = phi i64 [ %4, %do.end ], [ %a2, %entry ]
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%a1.addr.1 = phi ptr [ %add.ptr, %do.end ], [ %a1, %entry ]
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%5 = tail call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.i64(<vscale x 64 x i8> undef, ptr %a1.addr.1, i64 %t0.0)
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%6 = inttoptr i64 %a3.1 to ptr
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tail call void @llvm.riscv.vse.nxv64i8.i64(<vscale x 64 x i8> %5, ptr %6, i64 %t0.0)
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ret ptr %a0
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}
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declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg)
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declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.i64(<vscale x 64 x i8>, ptr nocapture, i64)
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declare void @llvm.riscv.vse.nxv64i8.i64(<vscale x 64 x i8>, ptr nocapture, i64)
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