a496c8be6e
And dependent commits. Details in D150388. This reverts commit825b7f0ca5. This reverts commit7a98f084c4. This reverts commitb4a62b1fa5. This reverts commitb7836d8562. No conflicts in the code, few tests had conflicts in autogenerated CHECKs: llvm/test/CodeGen/Thumb2/mve-float32regloops.ll llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll Reviewed By: alexfh Differential Revision: https://reviews.llvm.org/D156381
461 lines
16 KiB
C++
461 lines
16 KiB
C++
//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#include "llvm/IR/PassManager.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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class TargetMachine;
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// GlobalISel passes
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void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
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FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
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void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
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FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
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FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
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void initializeAMDGPURegBankCombinerPass(PassRegistry &);
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void initializeAMDGPURegBankSelectPass(PassRegistry &);
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// SI Passes
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FunctionPass *createGCNDPPCombinePass();
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FunctionPass *createSIAnnotateControlFlowPass();
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FunctionPass *createSIFoldOperandsPass();
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FunctionPass *createSIPeepholeSDWAPass();
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FunctionPass *createSILowerI1CopiesPass();
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FunctionPass *createSIShrinkInstructionsPass();
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FunctionPass *createSILoadStoreOptimizerPass();
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FunctionPass *createSIWholeQuadModePass();
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FunctionPass *createSIFixControlFlowLiveIntervalsPass();
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FunctionPass *createSIOptimizeExecMaskingPreRAPass();
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FunctionPass *createSIOptimizeVGPRLiveRangePass();
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FunctionPass *createSIFixSGPRCopiesPass();
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FunctionPass *createSIMemoryLegalizerPass();
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FunctionPass *createSIInsertWaitcntsPass();
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FunctionPass *createSIPreAllocateWWMRegsPass();
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FunctionPass *createSIFormMemoryClausesPass();
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FunctionPass *createSIPostRABundlerPass();
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FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *);
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FunctionPass *createAMDGPUUseNativeCallsPass();
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ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
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FunctionPass *createAMDGPUCodeGenPreparePass();
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FunctionPass *createAMDGPULateCodeGenPreparePass();
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FunctionPass *createAMDGPUMachineCFGStructurizerPass();
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FunctionPass *createAMDGPURewriteOutArgumentsPass();
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ModulePass *createAMDGPULowerModuleLDSPass();
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FunctionPass *createSIModeRegisterPass();
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FunctionPass *createGCNPreRAOptimizationsPass();
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struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
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AMDGPUSimplifyLibCallsPass(TargetMachine &TM) : TM(TM) {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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private:
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TargetMachine &TM;
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};
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struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
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void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
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extern char &AMDGPUMachineCFGStructurizerID;
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void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
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Pass *createAMDGPUAnnotateKernelFeaturesPass();
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Pass *createAMDGPUAttributorPass();
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void initializeAMDGPUAttributorPass(PassRegistry &);
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void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
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extern char &AMDGPUAnnotateKernelFeaturesID;
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// DPP/Iterative option enables the atomic optimizer with given strategy
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// whereas None disables the atomic optimizer.
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enum class ScanOptions { DPP, Iterative, None };
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FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
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void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
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extern char &AMDGPUAtomicOptimizerID;
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ModulePass *createAMDGPUCtorDtorLoweringLegacyPass();
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void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &);
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extern char &AMDGPUCtorDtorLoweringLegacyPassID;
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FunctionPass *createAMDGPULowerKernelArgumentsPass();
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void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
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extern char &AMDGPULowerKernelArgumentsID;
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FunctionPass *createAMDGPUPromoteKernelArgumentsPass();
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void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &);
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extern char &AMDGPUPromoteKernelArgumentsID;
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struct AMDGPUPromoteKernelArgumentsPass
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: PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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ModulePass *createAMDGPULowerKernelAttributesPass();
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void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
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extern char &AMDGPULowerKernelAttributesID;
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struct AMDGPULowerKernelAttributesPass
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: PassInfoMixin<AMDGPULowerKernelAttributesPass> {
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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void initializeAMDGPULowerModuleLDSPass(PassRegistry &);
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extern char &AMDGPULowerModuleLDSID;
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struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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};
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void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
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extern char &AMDGPURewriteOutArgumentsID;
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void initializeGCNDPPCombinePass(PassRegistry &);
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extern char &GCNDPPCombineID;
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void initializeSIFoldOperandsPass(PassRegistry &);
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extern char &SIFoldOperandsID;
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void initializeSIPeepholeSDWAPass(PassRegistry &);
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extern char &SIPeepholeSDWAID;
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void initializeSIShrinkInstructionsPass(PassRegistry&);
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extern char &SIShrinkInstructionsID;
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void initializeSIFixSGPRCopiesPass(PassRegistry &);
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extern char &SIFixSGPRCopiesID;
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void initializeSIFixVGPRCopiesPass(PassRegistry &);
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extern char &SIFixVGPRCopiesID;
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void initializeSILowerI1CopiesPass(PassRegistry &);
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extern char &SILowerI1CopiesID;
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void initializeSILowerSGPRSpillsPass(PassRegistry &);
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extern char &SILowerSGPRSpillsID;
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void initializeSILoadStoreOptimizerPass(PassRegistry &);
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extern char &SILoadStoreOptimizerID;
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void initializeSIWholeQuadModePass(PassRegistry &);
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extern char &SIWholeQuadModeID;
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void initializeSILowerControlFlowPass(PassRegistry &);
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extern char &SILowerControlFlowID;
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void initializeSIPreEmitPeepholePass(PassRegistry &);
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extern char &SIPreEmitPeepholeID;
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void initializeSILateBranchLoweringPass(PassRegistry &);
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extern char &SILateBranchLoweringPassID;
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void initializeSIOptimizeExecMaskingPass(PassRegistry &);
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extern char &SIOptimizeExecMaskingID;
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void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
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extern char &SIPreAllocateWWMRegsID;
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void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
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extern char &AMDGPUSimplifyLibCallsID;
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void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
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extern char &AMDGPUUseNativeCallsID;
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void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
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extern char &AMDGPUPerfHintAnalysisID;
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// Passes common to R600 and SI
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FunctionPass *createAMDGPUPromoteAlloca();
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void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
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extern char &AMDGPUPromoteAllocaID;
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FunctionPass *createAMDGPUPromoteAllocaToVector();
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void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&);
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extern char &AMDGPUPromoteAllocaToVectorID;
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struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
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AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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private:
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TargetMachine &TM;
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};
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struct AMDGPUPromoteAllocaToVectorPass
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: PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
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AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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private:
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TargetMachine &TM;
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};
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struct AMDGPUAtomicOptimizerPass : PassInfoMixin<AMDGPUAtomicOptimizerPass> {
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AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
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: TM(TM), ScanImpl(ScanImpl) {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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private:
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TargetMachine &TM;
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ScanOptions ScanImpl;
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};
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Pass *createAMDGPUStructurizeCFGPass();
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FunctionPass *createAMDGPUISelDag(TargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
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struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
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AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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private:
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bool GlobalOpt;
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};
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class AMDGPUCodeGenPreparePass
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: public PassInfoMixin<AMDGPUCodeGenPreparePass> {
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private:
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TargetMachine &TM;
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public:
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AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM){};
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PreservedAnalyses run(Function &, FunctionAnalysisManager &);
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};
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FunctionPass *createAMDGPUAnnotateUniformValues();
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ModulePass *createAMDGPUPrintfRuntimeBinding();
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void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
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extern char &AMDGPUPrintfRuntimeBindingID;
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void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &);
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extern char &AMDGPUResourceUsageAnalysisID;
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struct AMDGPUPrintfRuntimeBindingPass
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: PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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};
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ModulePass* createAMDGPUUnifyMetadataPass();
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void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
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extern char &AMDGPUUnifyMetadataID;
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struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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};
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void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
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extern char &SIOptimizeExecMaskingPreRAID;
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void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &);
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extern char &SIOptimizeVGPRLiveRangeID;
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void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
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extern char &AMDGPUAnnotateUniformValuesPassID;
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void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
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extern char &AMDGPUCodeGenPrepareID;
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void initializeAMDGPURemoveIncompatibleFunctionsPass(PassRegistry &);
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extern char &AMDGPURemoveIncompatibleFunctionsID;
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void initializeAMDGPULateCodeGenPreparePass(PassRegistry &);
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extern char &AMDGPULateCodeGenPrepareID;
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FunctionPass *createAMDGPURewriteUndefForPHIPass();
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void initializeAMDGPURewriteUndefForPHIPass(PassRegistry &);
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extern char &AMDGPURewriteUndefForPHIPassID;
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void initializeSIAnnotateControlFlowPass(PassRegistry&);
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extern char &SIAnnotateControlFlowPassID;
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void initializeSIMemoryLegalizerPass(PassRegistry&);
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extern char &SIMemoryLegalizerID;
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void initializeSIModeRegisterPass(PassRegistry&);
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extern char &SIModeRegisterID;
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void initializeAMDGPUInsertDelayAluPass(PassRegistry &);
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extern char &AMDGPUInsertDelayAluID;
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void initializeSIInsertHardClausesPass(PassRegistry &);
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extern char &SIInsertHardClausesID;
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void initializeSIInsertWaitcntsPass(PassRegistry&);
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extern char &SIInsertWaitcntsID;
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void initializeSIFormMemoryClausesPass(PassRegistry&);
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extern char &SIFormMemoryClausesID;
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void initializeSIPostRABundlerPass(PassRegistry&);
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extern char &SIPostRABundlerID;
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void initializeGCNCreateVOPDPass(PassRegistry &);
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extern char &GCNCreateVOPDID;
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void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
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extern char &AMDGPUUnifyDivergentExitNodesID;
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ImmutablePass *createAMDGPUAAWrapperPass();
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void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
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ImmutablePass *createAMDGPUExternalAAWrapperPass();
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void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
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void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
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ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
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void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
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extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
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void initializeGCNNSAReassignPass(PassRegistry &);
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extern char &GCNNSAReassignID;
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void initializeGCNPreRALongBranchRegPass(PassRegistry &);
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extern char &GCNPreRALongBranchRegID;
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void initializeGCNPreRAOptimizationsPass(PassRegistry &);
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extern char &GCNPreRAOptimizationsID;
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FunctionPass *createAMDGPUSetWavePriorityPass();
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void initializeAMDGPUSetWavePriorityPass(PassRegistry &);
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void initializeGCNRewritePartialRegUsesPass(llvm::PassRegistry &);
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extern char &GCNRewritePartialRegUsesID;
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namespace AMDGPU {
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enum TargetIndex {
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TI_CONSTDATA_START,
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TI_SCRATCH_RSRC_DWORD0,
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TI_SCRATCH_RSRC_DWORD1,
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TI_SCRATCH_RSRC_DWORD2,
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TI_SCRATCH_RSRC_DWORD3
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};
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}
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/// OpenCL uses address spaces to differentiate between
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/// various memory regions on the hardware. On the CPU
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/// all of the address spaces point to the same memory,
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/// however on the GPU, each address space points to
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/// a separate piece of memory that is unique from other
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/// memory locations.
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namespace AMDGPUAS {
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enum : unsigned {
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// The maximum value for flat, generic, local, private, constant and region.
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MAX_AMDGPU_ADDRESS = 8,
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FLAT_ADDRESS = 0, ///< Address space for flat memory.
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GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
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REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
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CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
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LOCAL_ADDRESS = 3, ///< Address space for local memory.
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PRIVATE_ADDRESS = 5, ///< Address space for private memory.
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CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
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BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
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///< Not used in backend.
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BUFFER_RESOURCE = 8, ///< Address space for 128-bit buffer resources.
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/// Internal address spaces. Can be freely renumbered.
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STREAMOUT_REGISTER = 128, ///< Address space for GS NGG Streamout registers.
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/// end Internal address spaces.
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/// Address space for direct addressable parameter memory (CONST0).
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PARAM_D_ADDRESS = 6,
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/// Address space for indirect addressable parameter memory (VTX1).
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PARAM_I_ADDRESS = 7,
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// Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
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// this order to be able to dynamically index a constant buffer, for
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// example:
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//
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// ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
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CONSTANT_BUFFER_0 = 8,
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CONSTANT_BUFFER_1 = 9,
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CONSTANT_BUFFER_2 = 10,
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CONSTANT_BUFFER_3 = 11,
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CONSTANT_BUFFER_4 = 12,
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CONSTANT_BUFFER_5 = 13,
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CONSTANT_BUFFER_6 = 14,
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CONSTANT_BUFFER_7 = 15,
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CONSTANT_BUFFER_8 = 16,
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CONSTANT_BUFFER_9 = 17,
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CONSTANT_BUFFER_10 = 18,
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CONSTANT_BUFFER_11 = 19,
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CONSTANT_BUFFER_12 = 20,
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CONSTANT_BUFFER_13 = 21,
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CONSTANT_BUFFER_14 = 22,
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CONSTANT_BUFFER_15 = 23,
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// Some places use this if the address space can't be determined.
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UNKNOWN_ADDRESS_SPACE = ~0u,
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};
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}
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namespace AMDGPU {
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// FIXME: Missing constant_32bit
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inline bool isFlatGlobalAddrSpace(unsigned AS) {
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return AS == AMDGPUAS::GLOBAL_ADDRESS ||
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AS == AMDGPUAS::FLAT_ADDRESS ||
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AS == AMDGPUAS::CONSTANT_ADDRESS ||
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AS > AMDGPUAS::MAX_AMDGPU_ADDRESS;
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}
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inline bool isExtendedGlobalAddrSpace(unsigned AS) {
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return AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::CONSTANT_ADDRESS ||
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AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
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AS > AMDGPUAS::MAX_AMDGPU_ADDRESS;
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}
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static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
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static_assert(AMDGPUAS::MAX_AMDGPU_ADDRESS <= 8, "Addr space out of range");
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if (AS1 > AMDGPUAS::MAX_AMDGPU_ADDRESS || AS2 > AMDGPUAS::MAX_AMDGPU_ADDRESS)
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return true;
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// This array is indexed by address space value enum elements 0 ... to 8
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// clang-format off
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static const bool ASAliasRules[9][9] = {
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/* Flat Global Region Group Constant Private Const32 BufFatPtr BufRsrc */
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/* Flat */ {true, true, false, true, true, true, true, true, true},
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/* Global */ {true, true, false, false, true, false, true, true, true},
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/* Region */ {false, false, true, false, false, false, false, false, false},
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/* Group */ {true, false, false, true, false, false, false, false, false},
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/* Constant */ {true, true, false, false, false, false, true, true, true},
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/* Private */ {true, false, false, false, false, true, false, false, false},
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/* Constant 32-bit */ {true, true, false, false, true, false, false, true, true},
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/* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true},
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/* Buffer Resource */ {true, true, false, false, true, false, true, true, true},
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};
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// clang-format on
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return ASAliasRules[AS1][AS2];
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}
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}
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} // End namespace llvm
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#endif
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