fb54afd1b7
This isn't always folded to fneg for a freestanding fsub depending on the denormal mode. When matching source modifiers, we're implicitly canonicalizing the input so we can fold it here. Doesn't bother handling the VOP3P case since it's only relevant with DAZ, which nobody really uses with f16. For f64, tests show an existing bug where DAGCombiner tries to respect the denormal mode for fsub -0, x, but not after it's lowered to fadd -0, (fneg x). Either the fold is wrong or we shouldn't restrict the fsub case based on the denormal mode. https://reviews.llvm.org/D155652
359 lines
14 KiB
C++
359 lines
14 KiB
C++
//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the InstructionSelector class for
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/// AMDGPU.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#include "SIDefines.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/IR/InstrTypes.h"
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namespace {
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#define AMDGPUSubtarget GCNSubtarget
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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#undef AMDGPUSubtarget
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}
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namespace llvm {
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namespace AMDGPU {
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struct ImageDimIntrinsicInfo;
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}
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class AMDGPURegisterBankInfo;
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class AMDGPUTargetMachine;
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class BlockFrequencyInfo;
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class ProfileSummaryInfo;
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class GCNSubtarget;
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class MachineInstr;
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class MachineIRBuilder;
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class MachineOperand;
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class MachineRegisterInfo;
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class RegisterBank;
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class SIInstrInfo;
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class SIRegisterInfo;
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class TargetRegisterClass;
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class AMDGPUInstructionSelector final : public InstructionSelector {
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private:
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MachineRegisterInfo *MRI;
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const GCNSubtarget *Subtarget;
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public:
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AMDGPUInstructionSelector(const GCNSubtarget &STI,
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const AMDGPURegisterBankInfo &RBI,
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const AMDGPUTargetMachine &TM);
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bool select(MachineInstr &I) override;
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static const char *getName();
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void setupMF(MachineFunction &MF, GISelKnownBits *KB,
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CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI,
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BlockFrequencyInfo *BFI) override;
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private:
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struct GEPInfo {
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SmallVector<unsigned, 2> SgprParts;
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SmallVector<unsigned, 2> VgprParts;
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int64_t Imm = 0;
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};
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bool isSGPR(Register Reg) const;
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bool isInstrUniform(const MachineInstr &MI) const;
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bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
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const RegisterBank *getArtifactRegBank(
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Register Reg, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) const;
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/// tblgen-erated 'select' implementation.
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bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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MachineOperand getSubOperand64(MachineOperand &MO,
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const TargetRegisterClass &SubRC,
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unsigned SubIdx) const;
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bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
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bool selectCOPY(MachineInstr &I) const;
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bool selectPHI(MachineInstr &I) const;
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bool selectG_TRUNC(MachineInstr &I) const;
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bool selectG_SZA_EXT(MachineInstr &I) const;
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bool selectG_CONSTANT(MachineInstr &I) const;
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bool selectG_FNEG(MachineInstr &I) const;
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bool selectG_FABS(MachineInstr &I) const;
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bool selectG_AND_OR_XOR(MachineInstr &I) const;
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bool selectG_ADD_SUB(MachineInstr &I) const;
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bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
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bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
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bool selectG_EXTRACT(MachineInstr &I) const;
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bool selectG_FMA_FMAD(MachineInstr &I) const;
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bool selectG_MERGE_VALUES(MachineInstr &I) const;
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bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
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bool selectG_BUILD_VECTOR(MachineInstr &I) const;
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bool selectG_PTR_ADD(MachineInstr &I) const;
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bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
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bool selectG_INSERT(MachineInstr &I) const;
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bool selectG_SBFX_UBFX(MachineInstr &I) const;
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bool selectInterpP1F16(MachineInstr &MI) const;
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bool selectWritelane(MachineInstr &MI) const;
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bool selectDivScale(MachineInstr &MI) const;
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bool selectIntrinsicCmp(MachineInstr &MI) const;
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bool selectBallot(MachineInstr &I) const;
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bool selectInverseBallot(MachineInstr &I) const;
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bool selectRelocConstant(MachineInstr &I) const;
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bool selectGroupStaticSize(MachineInstr &I) const;
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bool selectReturnAddress(MachineInstr &I) const;
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bool selectG_INTRINSIC(MachineInstr &I) const;
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bool selectEndCfIntrinsic(MachineInstr &MI) const;
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bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
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bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
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bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
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bool selectSBarrier(MachineInstr &MI) const;
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bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
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bool selectImageIntrinsic(MachineInstr &MI,
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const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
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bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
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int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
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bool selectG_ICMP(MachineInstr &I) const;
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bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
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void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
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SmallVectorImpl<GEPInfo> &AddrInfo) const;
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void initM0(MachineInstr &I) const;
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bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
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bool selectG_SELECT(MachineInstr &I) const;
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bool selectG_BRCOND(MachineInstr &I) const;
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bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
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bool selectG_PTRMASK(MachineInstr &I) const;
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bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
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bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
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bool selectBufferLoadLds(MachineInstr &MI) const;
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bool selectGlobalLoadLds(MachineInstr &MI) const;
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bool selectBVHIntrinsic(MachineInstr &I) const;
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bool selectSMFMACIntrin(MachineInstr &I) const;
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bool selectWaveAddress(MachineInstr &I) const;
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std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
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bool IsCanonicalizing = true,
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bool AllowAbs = true,
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bool OpSel = false) const;
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Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
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MachineOperand Root, MachineInstr *InsertPt,
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bool ForceVGPR = false) const;
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InstructionSelector::ComplexRendererFns
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selectVCSRC(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVSRC0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3BMods0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3OMods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3BMods(MachineOperand &Root) const;
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ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
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std::pair<Register, unsigned>
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selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
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bool IsDOT = false) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3PMods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3PModsDOT(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectDotIUVOP3PMods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3OpSelMods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVINTERPMods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVINTERPModsHi(MachineOperand &Root) const;
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bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
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int64_t *Offset) const;
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InstructionSelector::ComplexRendererFns
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selectSmrdImm(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectSmrdImm32(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectSmrdSgpr(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectSmrdSgprImm(MachineOperand &Root) const;
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std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
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uint64_t FlatVariant) const;
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InstructionSelector::ComplexRendererFns
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selectFlatOffset(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectGlobalOffset(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectScratchOffset(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectGlobalSAddr(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectScratchSAddr(MachineOperand &Root) const;
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bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
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uint64_t ImmOffset) const;
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InstructionSelector::ComplexRendererFns
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selectScratchSVAddr(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectMUBUFScratchOffen(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectMUBUFScratchOffset(MachineOperand &Root) const;
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bool isDSOffsetLegal(Register Base, int64_t Offset) const;
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bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
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unsigned Size) const;
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bool isFlatScratchBaseLegal(
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Register Base, uint64_t FlatVariant = SIInstrFlags::FlatScratch) const;
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std::pair<Register, unsigned>
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selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectDS1Addr1Offset(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectDS64Bit4ByteAligned(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectDS128Bit8ByteAligned(MachineOperand &Root) const;
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std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
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unsigned size) const;
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InstructionSelector::ComplexRendererFns
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selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
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std::pair<Register, int64_t>
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getPtrBaseWithConstantOffset(Register Root,
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const MachineRegisterInfo &MRI) const;
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// Parse out a chain of up to two g_ptr_add instructions.
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// g_ptr_add (n0, _)
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// g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
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struct MUBUFAddressData {
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Register N0, N2, N3;
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int64_t Offset = 0;
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};
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bool shouldUseAddr64(MUBUFAddressData AddrData) const;
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void splitIllegalMUBUFOffset(MachineIRBuilder &B,
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Register &SOffset, int64_t &ImmOffset) const;
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MUBUFAddressData parseMUBUFAddress(Register Src) const;
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bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
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Register &RSrcReg, Register &SOffset,
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int64_t &Offset) const;
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bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
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Register &SOffset, int64_t &Offset) const;
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InstructionSelector::ComplexRendererFns
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selectMUBUFAddr64(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectMUBUFOffset(MachineOperand &Root) const;
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ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
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ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
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ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
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std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
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bool &Matched) const;
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ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
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ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
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void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx = -1) const;
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void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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bool isInlineImmediate16(int64_t Imm) const;
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bool isInlineImmediate32(int64_t Imm) const;
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bool isInlineImmediate64(int64_t Imm) const;
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bool isInlineImmediate(const APFloat &Imm) const;
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// Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
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// shift amount operand's `ShAmtBits` bits is unneeded.
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bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
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const SIInstrInfo &TII;
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const SIRegisterInfo &TRI;
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const AMDGPURegisterBankInfo &RBI;
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const AMDGPUTargetMachine &TM;
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const GCNSubtarget &STI;
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bool EnableLateStructurizeCFG;
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#define GET_GLOBALISEL_PREDICATES_DECL
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#define AMDGPUSubtarget GCNSubtarget
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_DECL
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#undef AMDGPUSubtarget
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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};
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} // End llvm namespace.
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#endif
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