76c22b18ea
Correct AMDGPU strictfp tests to follow the rules documented in the LangRef: https://llvm.org/docs/LangRef.html#constrained-floating-point-intrinsics Mostly these tests just needed the strictfp attribute on function definitions. I've also removed the strictfp attribute from uses of the constrained intrinsics because it comes by default since D154991, but I only did this in tests I was changing anyway. I also removed attributes added to declare lines of intrinsics. The attributes of intrinsics cannot be changed in a test so I eliminated attempts to do so. Test changes verified with D146845.
3267 lines
135 KiB
LLVM
3267 lines
135 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx704 < %s | FileCheck --check-prefixes=GFX7CHECK,GFX7SELDAG %s
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; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx704 < %s | FileCheck --check-prefixes=GFX7CHECK,GFX7GLISEL %s
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; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx803 < %s | FileCheck --check-prefixes=GFX8CHECK,GFX8SELDAG %s
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; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx803 < %s | FileCheck --check-prefixes=GFX8CHECK,GFX8GLISEL %s
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; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefixes=GFX9CHECK,GFX9SELDAG %s
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; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefixes=GFX9CHECK,GFX9GLISEL %s
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; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1031 < %s | FileCheck --check-prefixes=GFX10CHECK,GFX10SELDAG %s
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; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1031 < %s | FileCheck --check-prefixes=GFX10CHECK,GFX10GLISEL %s
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; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX11CHECK,GFX11SELDAG %s
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; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX11CHECK,GFX11GLISEL %s
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define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
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; GFX7SELDAG-LABEL: sgpr_isnan_f16:
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; GFX7SELDAG: ; %bb.0:
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; GFX7SELDAG-NEXT: s_load_dword s4, s[0:1], 0xb
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; GFX7SELDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GFX7SELDAG-NEXT: s_mov_b32 s3, 0xf000
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; GFX7SELDAG-NEXT: s_mov_b32 s2, -1
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; GFX7SELDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7SELDAG-NEXT: s_and_b32 s4, s4, 0x7fff
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; GFX7SELDAG-NEXT: s_cmpk_gt_i32 s4, 0x7c00
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; GFX7SELDAG-NEXT: s_cselect_b64 s[4:5], -1, 0
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; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]
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; GFX7SELDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7SELDAG-NEXT: s_endpgm
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;
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; GFX7GLISEL-LABEL: sgpr_isnan_f16:
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; GFX7GLISEL: ; %bb.0:
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; GFX7GLISEL-NEXT: s_load_dword s3, s[0:1], 0xb
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; GFX7GLISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GFX7GLISEL-NEXT: s_mov_b32 s2, -1
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; GFX7GLISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7GLISEL-NEXT: s_and_b32 s3, s3, 0x7fff
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; GFX7GLISEL-NEXT: s_and_b32 s3, 0xffff, s3
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; GFX7GLISEL-NEXT: s_cmpk_gt_u32 s3, 0x7c00
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; GFX7GLISEL-NEXT: s_cselect_b32 s3, 1, 0
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; GFX7GLISEL-NEXT: s_bfe_i32 s3, s3, 0x10000
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; GFX7GLISEL-NEXT: v_mov_b32_e32 v0, s3
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; GFX7GLISEL-NEXT: s_mov_b32 s3, 0xf000
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; GFX7GLISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7GLISEL-NEXT: s_endpgm
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;
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; GFX8CHECK-LABEL: sgpr_isnan_f16:
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; GFX8CHECK: ; %bb.0:
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; GFX8CHECK-NEXT: s_load_dword s2, s[0:1], 0x2c
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; GFX8CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX8CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[2:3], s2, 3
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; GFX8CHECK-NEXT: v_mov_b32_e32 v0, s0
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; GFX8CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[2:3]
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; GFX8CHECK-NEXT: v_mov_b32_e32 v1, s1
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; GFX8CHECK-NEXT: flat_store_dword v[0:1], v2
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; GFX8CHECK-NEXT: s_endpgm
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;
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; GFX9CHECK-LABEL: sgpr_isnan_f16:
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; GFX9CHECK: ; %bb.0:
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; GFX9CHECK-NEXT: s_load_dword s4, s[0:1], 0x2c
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; GFX9CHECK-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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; GFX9CHECK-NEXT: v_mov_b32_e32 v0, 0
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; GFX9CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[0:1], s4, 3
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; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[0:1]
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; GFX9CHECK-NEXT: global_store_dword v0, v1, s[2:3]
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; GFX9CHECK-NEXT: s_endpgm
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;
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; GFX10CHECK-LABEL: sgpr_isnan_f16:
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; GFX10CHECK: ; %bb.0:
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; GFX10CHECK-NEXT: s_clause 0x1
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; GFX10CHECK-NEXT: s_load_dword s2, s[0:1], 0x2c
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; GFX10CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX10CHECK-NEXT: v_mov_b32_e32 v0, 0
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; GFX10CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s2, s2, 3
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; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
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; GFX10CHECK-NEXT: global_store_dword v0, v1, s[0:1]
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; GFX10CHECK-NEXT: s_endpgm
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;
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; GFX11CHECK-LABEL: sgpr_isnan_f16:
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; GFX11CHECK: ; %bb.0:
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; GFX11CHECK-NEXT: s_clause 0x1
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; GFX11CHECK-NEXT: s_load_b32 s2, s[0:1], 0x2c
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; GFX11CHECK-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11CHECK-NEXT: v_mov_b32_e32 v0, 0
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; GFX11CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s2, s2, 3
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; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
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; GFX11CHECK-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11CHECK-NEXT: s_nop 0
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; GFX11CHECK-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11CHECK-NEXT: s_endpgm
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%result = call i1 @llvm.is.fpclass.f16(half %x, i32 3)
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%sext = sext i1 %result to i32
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store i32 %sext, ptr addrspace(1) %out, align 4
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ret void
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}
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define i1 @zeromask_f16(half %x) nounwind {
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; GFX7CHECK-LABEL: zeromask_f16:
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; GFX7CHECK: ; %bb.0:
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; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7CHECK-NEXT: v_mov_b32_e32 v0, 0
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; GFX7CHECK-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8CHECK-LABEL: zeromask_f16:
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; GFX8CHECK: ; %bb.0:
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; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8CHECK-NEXT: v_mov_b32_e32 v0, 0
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; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9CHECK-LABEL: zeromask_f16:
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; GFX9CHECK: ; %bb.0:
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; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9CHECK-NEXT: v_mov_b32_e32 v0, 0
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; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10CHECK-LABEL: zeromask_f16:
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; GFX10CHECK: ; %bb.0:
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; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10CHECK-NEXT: v_mov_b32_e32 v0, 0
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; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11CHECK-LABEL: zeromask_f16:
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; GFX11CHECK: ; %bb.0:
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; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11CHECK-NEXT: v_mov_b32_e32 v0, 0
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; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
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%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 0)
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ret i1 %1
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}
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; FIXME: DAG and GlobalISel return different values for i1 true
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define i1 @allflags_f16(half %x) nounwind {
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; GFX7SELDAG-LABEL: allflags_f16:
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; GFX7SELDAG: ; %bb.0:
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; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7SELDAG-NEXT: v_mov_b32_e32 v0, 1
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; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7GLISEL-LABEL: allflags_f16:
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; GFX7GLISEL: ; %bb.0:
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; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7GLISEL-NEXT: v_mov_b32_e32 v0, -1
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; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8SELDAG-LABEL: allflags_f16:
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; GFX8SELDAG: ; %bb.0:
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; GFX8SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8SELDAG-NEXT: v_mov_b32_e32 v0, 1
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; GFX8SELDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8GLISEL-LABEL: allflags_f16:
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; GFX8GLISEL: ; %bb.0:
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; GFX8GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8GLISEL-NEXT: v_mov_b32_e32 v0, -1
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; GFX8GLISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9SELDAG-LABEL: allflags_f16:
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; GFX9SELDAG: ; %bb.0:
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; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9SELDAG-NEXT: v_mov_b32_e32 v0, 1
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; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9GLISEL-LABEL: allflags_f16:
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; GFX9GLISEL: ; %bb.0:
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; GFX9GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9GLISEL-NEXT: v_mov_b32_e32 v0, -1
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; GFX9GLISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10SELDAG-LABEL: allflags_f16:
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; GFX10SELDAG: ; %bb.0:
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; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10SELDAG-NEXT: v_mov_b32_e32 v0, 1
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; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10GLISEL-LABEL: allflags_f16:
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; GFX10GLISEL: ; %bb.0:
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; GFX10GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, -1
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; GFX10GLISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11SELDAG-LABEL: allflags_f16:
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; GFX11SELDAG: ; %bb.0:
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; GFX11SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11SELDAG-NEXT: v_mov_b32_e32 v0, 1
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; GFX11SELDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11GLISEL-LABEL: allflags_f16:
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; GFX11GLISEL: ; %bb.0:
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; GFX11GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11GLISEL-NEXT: v_mov_b32_e32 v0, -1
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; GFX11GLISEL-NEXT: s_setpc_b64 s[30:31]
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%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 1023) ; 0x3ff
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ret i1 %1
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}
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define i1 @snan_f16(half %x) nounwind {
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; GFX7SELDAG-LABEL: snan_f16:
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; GFX7SELDAG: ; %bb.0:
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; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7e00
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; GFX7SELDAG-NEXT: s_movk_i32 s5, 0x7c00
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; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
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; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s5, v0
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; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
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; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
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; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7GLISEL-LABEL: snan_f16:
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; GFX7GLISEL: ; %bb.0:
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; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
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; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
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; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00
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; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1
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; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
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; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
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; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8CHECK-LABEL: snan_f16:
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; GFX8CHECK: ; %bb.0:
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; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 1
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; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
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; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9CHECK-LABEL: snan_f16:
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; GFX9CHECK: ; %bb.0:
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; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 1
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; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
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; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10CHECK-LABEL: snan_f16:
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; GFX10CHECK: ; %bb.0:
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; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 1
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; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
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; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11CHECK-LABEL: snan_f16:
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; GFX11CHECK: ; %bb.0:
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; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 1
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; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
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; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
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%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 1) ; 0x001
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ret i1 %1
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}
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define i1 @qnan_f16(half %x) nounwind {
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; GFX7SELDAG-LABEL: qnan_f16:
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; GFX7SELDAG: ; %bb.0:
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; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7dff
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; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
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; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX7GLISEL-LABEL: qnan_f16:
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; GFX7GLISEL: ; %bb.0:
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; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00
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; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
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; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8CHECK-LABEL: qnan_f16:
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; GFX8CHECK: ; %bb.0:
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; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 2
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: qnan_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 2
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: qnan_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 2
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: qnan_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 2
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 2) ; 0x002
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @posinf_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: posinf_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: posinf_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: posinf_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x200
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: posinf_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x200
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: posinf_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x200
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: posinf_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x200
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 512) ; 0x200
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @neginf_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: neginf_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_mov_b32 s4, 0xfc00
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: neginf_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xfc00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: neginf_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 4
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: neginf_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 4
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: neginf_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 4
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: neginf_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 4
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 4) ; 0x004
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @posnormal_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: posnormal_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
|
|
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: posnormal_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v2
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: posnormal_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x100
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: posnormal_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x100
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: posnormal_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x100
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: posnormal_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x100
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 256) ; 0x100
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @negnormal_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: negnormal_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
|
|
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: negnormal_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v0, v2
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: negnormal_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 8
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: negnormal_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 8
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: negnormal_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 8
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: negnormal_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 8
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 8) ; 0x008
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @possubnormal_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: possubnormal_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, -1, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: possubnormal_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 1, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x3ff
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: possubnormal_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x80
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: possubnormal_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x80
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: possubnormal_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x80
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: possubnormal_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x80
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 128) ; 0x080
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @negsubnormal_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: negsubnormal_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_add_i32_e64 v0, s[4:5], -1, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v0
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: negsubnormal_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v2
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e64 v0, s[4:5], 1, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x3ff
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1
|
|
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: negsubnormal_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 16
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: negsubnormal_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 16
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: negsubnormal_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 16
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: negsubnormal_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 16
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 16) ; 0x010
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @poszero_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: poszero_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: poszero_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: poszero_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 64
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: poszero_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 64
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: poszero_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 64
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: poszero_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 64
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 64) ; 0x040
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @negzero_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: negzero_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_mov_b32 s4, 0x8000
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: negzero_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x8000
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: negzero_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 32
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: negzero_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 32
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: negzero_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 32
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: negzero_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 32
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 32) ; 0x020
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @posfinite_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: posfinite_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: posfinite_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: posfinite_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x1c0
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: posfinite_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x1c0
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: posfinite_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x1c0
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: posfinite_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1c0
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 448) ; 0x1c0
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @negfinite_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: negfinite_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v0
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: negfinite_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v0, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v0
|
|
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: negfinite_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 56
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: negfinite_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 56
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: negfinite_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 56
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: negfinite_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 56
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 56) ; 0x038
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @isnan_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: isnan_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isnan_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: isnan_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: isnan_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: isnan_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 3
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: isnan_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3) ; nan
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @not_isnan_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_isnan_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_isnan_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, v0
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_isnan_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x3fc
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_isnan_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x3fc
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_isnan_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x3fc
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_isnan_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x3fc
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = call i1 @llvm.is.fpclass.f16(half %x, i32 1020) ; ~nan
|
|
ret i1 %class
|
|
}
|
|
|
|
define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
|
|
; GFX7SELDAG-LABEL: isnan_v2f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v1, 0x7fff, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v1
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isnan_v2f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: isnan_v2f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: isnan_v2f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 3
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, v1 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v0, v2
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: isnan_v2f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_mov_b32_e32 v1, 3
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 3
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_sdwa s4, v0, v1 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX10CHECK-NEXT: v_mov_b32_e32 v0, v2
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: isnan_v2f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v1, 3
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 3) ; nan
|
|
ret <2 x i1> %1
|
|
}
|
|
|
|
define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
|
|
; GFX7SELDAG-LABEL: isnan_v3f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v1, 0x7fff, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v2
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v1
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v2
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isnan_v3f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8SELDAG-LABEL: isnan_v3f16:
|
|
; GFX8SELDAG: ; %bb.0:
|
|
; GFX8SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8SELDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
|
|
; GFX8SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v2, v2
|
|
; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
|
|
; GFX8SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v0, v0
|
|
; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v1, v1
|
|
; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
|
|
; GFX8SELDAG-NEXT: v_mov_b32_e32 v1, v3
|
|
; GFX8SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8GLISEL-LABEL: isnan_v3f16:
|
|
; GFX8GLISEL: ; %bb.0:
|
|
; GFX8GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8GLISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
|
|
; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v2, 3
|
|
; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
|
|
; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
|
|
; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
|
|
; GFX8GLISEL-NEXT: v_mov_b32_e32 v1, v3
|
|
; GFX8GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9SELDAG-LABEL: isnan_v3f16:
|
|
; GFX9SELDAG: ; %bb.0:
|
|
; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9SELDAG-NEXT: v_cmp_u_f16_sdwa s[4:5], v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v0, v0
|
|
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
|
|
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v1, v1
|
|
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
|
|
; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, v3
|
|
; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9GLISEL-LABEL: isnan_v3f16:
|
|
; GFX9GLISEL: ; %bb.0:
|
|
; GFX9GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9GLISEL-NEXT: v_mov_b32_e32 v2, 3
|
|
; GFX9GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
|
|
; GFX9GLISEL-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, v2 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
|
|
; GFX9GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
|
|
; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
|
|
; GFX9GLISEL-NEXT: v_mov_b32_e32 v0, v4
|
|
; GFX9GLISEL-NEXT: v_mov_b32_e32 v1, v3
|
|
; GFX9GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10SELDAG-LABEL: isnan_v3f16:
|
|
; GFX10SELDAG: ; %bb.0:
|
|
; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10SELDAG-NEXT: v_cmp_u_f16_sdwa s4, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
|
|
; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
|
|
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
|
|
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
|
|
; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v1
|
|
; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, v3
|
|
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
|
|
; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10GLISEL-LABEL: isnan_v3f16:
|
|
; GFX10GLISEL: ; %bb.0:
|
|
; GFX10GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10GLISEL-NEXT: v_mov_b32_e32 v2, 3
|
|
; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v0, 3
|
|
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
|
|
; GFX10GLISEL-NEXT: v_cmp_class_f16_sdwa s4, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, v4
|
|
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
|
|
; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v1, 3
|
|
; GFX10GLISEL-NEXT: v_mov_b32_e32 v1, v3
|
|
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
|
|
; GFX10GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11SELDAG-LABEL: isnan_v3f16:
|
|
; GFX11SELDAG: ; %bb.0:
|
|
; GFX11SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11SELDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
|
|
; GFX11SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
|
|
; GFX11SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
|
|
; GFX11SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v2, v2
|
|
; GFX11SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
|
|
; GFX11SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v1
|
|
; GFX11SELDAG-NEXT: v_mov_b32_e32 v1, v3
|
|
; GFX11SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
|
|
; GFX11SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11GLISEL-LABEL: isnan_v3f16:
|
|
; GFX11GLISEL: ; %bb.0:
|
|
; GFX11GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11GLISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
|
|
; GFX11GLISEL-NEXT: v_cmp_class_f16_e64 s0, v0, 3
|
|
; GFX11GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11GLISEL-NEXT: v_cmp_class_f16_e64 s0, v2, 3
|
|
; GFX11GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
|
|
; GFX11GLISEL-NEXT: v_cmp_class_f16_e64 s0, v1, 3
|
|
; GFX11GLISEL-NEXT: v_mov_b32_e32 v1, v3
|
|
; GFX11GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
|
|
; GFX11GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call <3 x i1> @llvm.is.fpclass.v3f16(<3 x half> %x, i32 3) ; nan
|
|
ret <3 x i1> %1
|
|
}
|
|
|
|
define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
|
|
; GFX7SELDAG-LABEL: isnan_v4f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v1, 0x7fff, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v2
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v1
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v3, 0x7fff, v3
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v2
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v3
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isnan_v4f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0x7fff, v3
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v3
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8SELDAG-LABEL: isnan_v4f16:
|
|
; GFX8SELDAG: ; %bb.0:
|
|
; GFX8SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX8SELDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
|
|
; GFX8SELDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v1
|
|
; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
|
|
; GFX8SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v3, 3
|
|
; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
|
|
; GFX8SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v4, 3
|
|
; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
|
|
; GFX8SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8GLISEL-LABEL: isnan_v4f16:
|
|
; GFX8GLISEL: ; %bb.0:
|
|
; GFX8GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8GLISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
|
|
; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v2, 3
|
|
; GFX8GLISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
|
|
; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
|
|
; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
|
|
; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
|
|
; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v3, 3
|
|
; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
|
|
; GFX8GLISEL-NEXT: v_mov_b32_e32 v1, v4
|
|
; GFX8GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9SELDAG-LABEL: isnan_v4f16:
|
|
; GFX9SELDAG: ; %bb.0:
|
|
; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX9SELDAG-NEXT: v_mov_b32_e32 v3, 3
|
|
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
|
|
; GFX9SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
|
|
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
|
|
; GFX9SELDAG-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, v3 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
|
|
; GFX9SELDAG-NEXT: v_cmp_class_f16_sdwa s[4:5], v1, v3 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
|
|
; GFX9SELDAG-NEXT: v_mov_b32_e32 v0, v5
|
|
; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, v4
|
|
; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9GLISEL-LABEL: isnan_v4f16:
|
|
; GFX9GLISEL: ; %bb.0:
|
|
; GFX9GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9GLISEL-NEXT: v_mov_b32_e32 v3, 3
|
|
; GFX9GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
|
|
; GFX9GLISEL-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, v3 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
|
|
; GFX9GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
|
|
; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
|
|
; GFX9GLISEL-NEXT: v_cmp_class_f16_sdwa s[4:5], v1, v3 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
|
|
; GFX9GLISEL-NEXT: v_mov_b32_e32 v0, v4
|
|
; GFX9GLISEL-NEXT: v_mov_b32_e32 v1, v5
|
|
; GFX9GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10SELDAG-LABEL: isnan_v4f16:
|
|
; GFX10SELDAG: ; %bb.0:
|
|
; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10SELDAG-NEXT: v_mov_b32_e32 v2, 3
|
|
; GFX10SELDAG-NEXT: v_cmp_class_f16_e64 s5, v0, 3
|
|
; GFX10SELDAG-NEXT: v_cmp_class_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
|
|
; GFX10SELDAG-NEXT: v_cmp_class_f16_sdwa s5, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
|
|
; GFX10SELDAG-NEXT: v_mov_b32_e32 v0, v4
|
|
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, s5
|
|
; GFX10SELDAG-NEXT: v_cmp_class_f16_e64 s5, v1, 3
|
|
; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, v5
|
|
; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s5
|
|
; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10GLISEL-LABEL: isnan_v4f16:
|
|
; GFX10GLISEL: ; %bb.0:
|
|
; GFX10GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10GLISEL-NEXT: v_mov_b32_e32 v3, 3
|
|
; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v0, 3
|
|
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
|
|
; GFX10GLISEL-NEXT: v_cmp_class_f16_sdwa s4, v0, v3 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, v4
|
|
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
|
|
; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v1, 3
|
|
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
|
|
; GFX10GLISEL-NEXT: v_cmp_class_f16_sdwa s4, v1, v3 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX10GLISEL-NEXT: v_mov_b32_e32 v1, v5
|
|
; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
|
|
; GFX10GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: isnan_v4f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
|
|
; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v4, 16, v1
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v1, 3
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v3, 3
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v4, 3
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call <4 x i1> @llvm.is.fpclass.v4f16(<4 x half> %x, i32 3) ; nan
|
|
ret <4 x i1> %1
|
|
}
|
|
|
|
define i1 @isnan_f16_strictfp(half %x) strictfp nounwind {
|
|
; GFX7SELDAG-LABEL: isnan_f16_strictfp:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isnan_f16_strictfp:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: isnan_f16_strictfp:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: isnan_f16_strictfp:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: isnan_f16_strictfp:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 3
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: isnan_f16_strictfp:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3) strictfp ; nan
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @isinf_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: isinf_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isinf_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: isinf_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x204
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: isinf_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x204
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: isinf_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x204
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: isinf_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x204
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 516) ; 0x204 = "inf"
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @isfinite_f16(half %x) nounwind {
|
|
; GFX7SELDAG-LABEL: isfinite_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isfinite_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: isfinite_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x1f8
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: isfinite_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x1f8
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: isfinite_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x1f8
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: isfinite_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1f8
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 504) ; 0x1f8 = "finite"
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @issubnormal_or_zero_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: issubnormal_or_zero_f16:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7c00, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: issubnormal_or_zero_f16:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: issubnormal_or_zero_f16:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0xf0
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: issubnormal_or_zero_f16:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0xf0
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: issubnormal_or_zero_f16:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0xf0
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: issubnormal_or_zero_f16:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0xf0
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 240) ; 0xf0 = "subnormal|zero"
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @not_issubnormal_or_zero_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_issubnormal_or_zero_f16:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7c00, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_issubnormal_or_zero_f16:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_issubnormal_or_zero_f16:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x30f
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_issubnormal_or_zero_f16:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x30f
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_issubnormal_or_zero_f16:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x30f
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_issubnormal_or_zero_f16:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x30f
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @isnormal_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: isnormal_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7800
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isnormal_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: isnormal_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x108
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: isnormal_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x108
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: isnormal_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x108
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: isnormal_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x108
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 264) ; 0x108 = "normal"
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @not_isnormal_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_isnormal_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x77ff
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_isnormal_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v0
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_isnormal_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x2f7
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_isnormal_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x2f7
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_isnormal_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x2f7
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_isnormal_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x2f7
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 759) ; ~0x108 = "~normal"
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @not_is_plus_normal_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_is_plus_normal_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x77ff
|
|
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_is_plus_normal_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], s8, v3
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v3
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v2, v3
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_is_plus_normal_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x2ff
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_is_plus_normal_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x2ff
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_is_plus_normal_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x2ff
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_is_plus_normal_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x2ff
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 767) ; ~0x100 = ~"+normal"
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @not_is_neg_normal_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_is_neg_normal_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x77ff
|
|
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_is_neg_normal_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], s8, v3
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v3
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v2, v3
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_is_neg_normal_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x3f7
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_is_neg_normal_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x3f7
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_is_neg_normal_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x3f7
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_is_neg_normal_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x3f7
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 1015) ; ~0x008 = ~"-normal"
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @issubnormal_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: issubnormal_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, -1, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: issubnormal_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 1, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x3ff
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: issubnormal_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x90
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: issubnormal_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x90
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: issubnormal_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x90
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: issubnormal_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x90
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 144) ; 0x90 = "subnormal"
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @not_issubnormal_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_issubnormal_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3fe
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, -1, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_issubnormal_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_issubnormal_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x36f
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_issubnormal_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x36f
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_issubnormal_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x36f
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_issubnormal_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x36f
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 879) ; ~0x90 = ~"subnormal"
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @iszero_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: iszero_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: iszero_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: iszero_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x60
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: iszero_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x60
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: iszero_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x60
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: iszero_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x60
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 96) ; 0x60 = "zero"
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @not_iszero_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_iszero_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_iszero_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_iszero_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39f
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_iszero_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39f
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_iszero_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39f
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_iszero_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39f
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 927) ; ~0x60 = ~"zero"
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @ispositive_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: ispositive_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: ispositive_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, v0
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: ispositive_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x3c0
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: ispositive_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x3c0
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: ispositive_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x3c0
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: ispositive_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x3c0
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 960) ; fcPositive
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @not_ispositive_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_ispositive_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7c00
|
|
; GFX7SELDAG-NEXT: s_mov_b32 s7, 0xfc00
|
|
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s6, v2
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s7, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s6, v2
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_ispositive_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], s6, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0xfc00
|
|
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_ispositive_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 63
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_ispositive_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 63
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_ispositive_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 63
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_ispositive_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 63
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 63) ; ~fcPositive
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @isnegative_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: isnegative_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: s_mov_b32 s6, 0xfc00
|
|
; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v2
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s6, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isnegative_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xfc00
|
|
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: isnegative_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 60
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: isnegative_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 60
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: isnegative_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 60
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: isnegative_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 60
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 60) ; fcNegative
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @not_isnegative_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_isnegative_f16:
|
|
; GFX7SELDAG: ; %bb.0:
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s5, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s5, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_isnegative_f16:
|
|
; GFX7GLISEL: ; %bb.0:
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_isnegative_f16:
|
|
; GFX8CHECK: ; %bb.0:
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x3c3
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_isnegative_f16:
|
|
; GFX9CHECK: ; %bb.0:
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x3c3
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_isnegative_f16:
|
|
; GFX10CHECK: ; %bb.0:
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x3c3
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_isnegative_f16:
|
|
; GFX11CHECK: ; %bb.0:
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x3c3
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 963) ; ~fcNegative
|
|
ret i1 %class
|
|
}
|
|
|
|
define i1 @iszero_or_nan_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: iszero_or_nan_f16:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: iszero_or_nan_f16:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: iszero_or_nan_f16:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x63
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: iszero_or_nan_f16:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x63
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: iszero_or_nan_f16:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x63
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: iszero_or_nan_f16:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x63
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 99) ; 0x60|0x3 = "zero|nan"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @iszero_or_nan_f_daz(half %x) #0 {
|
|
; GFX7SELDAG-LABEL: iszero_or_nan_f_daz:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: iszero_or_nan_f_daz:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: iszero_or_nan_f_daz:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x63
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: iszero_or_nan_f_daz:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x63
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: iszero_or_nan_f_daz:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x63
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: iszero_or_nan_f_daz:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x63
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 99) ; 0x60|0x3 = "zero|nan"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @iszero_or_nan_f_maybe_daz(half %x) #1 {
|
|
; GFX7SELDAG-LABEL: iszero_or_nan_f_maybe_daz:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: iszero_or_nan_f_maybe_daz:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: iszero_or_nan_f_maybe_daz:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x63
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: iszero_or_nan_f_maybe_daz:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x63
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: iszero_or_nan_f_maybe_daz:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x63
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: iszero_or_nan_f_maybe_daz:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x63
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 99) ; 0x60|0x3 = "zero|nan"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @not_iszero_or_nan_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_iszero_or_nan_f16:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_iszero_or_nan_f16:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_iszero_or_nan_f16:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_iszero_or_nan_f16:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_iszero_or_nan_f16:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39c
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_iszero_or_nan_f16:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39c
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 924) ; ~0x60 = "~(zero|nan)"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @not_iszero_or_nan_f_daz(half %x) #0 {
|
|
; GFX7SELDAG-LABEL: not_iszero_or_nan_f_daz:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_iszero_or_nan_f_daz:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_iszero_or_nan_f_daz:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_iszero_or_nan_f_daz:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_iszero_or_nan_f_daz:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39c
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_iszero_or_nan_f_daz:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39c
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 924) ; ~(0x60|0x3) = "~(zero|nan)"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @not_iszero_or_nan_f_maybe_daz(half %x) #1 {
|
|
; GFX7SELDAG-LABEL: not_iszero_or_nan_f_maybe_daz:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_iszero_or_nan_f_maybe_daz:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_iszero_or_nan_f_maybe_daz:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_iszero_or_nan_f_maybe_daz:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_iszero_or_nan_f_maybe_daz:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39c
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_iszero_or_nan_f_maybe_daz:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39c
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 924) ; ~(0x60|0x3) = "~(zero|nan)"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @iszero_or_qnan_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: iszero_or_qnan_f16:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7dff
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: iszero_or_qnan_f16:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: iszero_or_qnan_f16:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x62
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: iszero_or_qnan_f16:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x62
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: iszero_or_qnan_f16:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x62
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: iszero_or_qnan_f16:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x62
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 98) ; 0x60|0x2 = "zero|qnan"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @iszero_or_snan_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: iszero_or_snan_f16:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7e00
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s5, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s5, v0
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: iszero_or_snan_f16:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[6:7], v0, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
|
|
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: iszero_or_snan_f16:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x61
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: iszero_or_snan_f16:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x61
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: iszero_or_snan_f16:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x61
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: iszero_or_snan_f16:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x61
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 97) ; 0x60|0x1 = "zero|snan"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @not_iszero_or_qnan_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_iszero_or_qnan_f16:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7e00
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s8, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s8, v0
|
|
; GFX7SELDAG-NEXT: s_and_b64 s[6:7], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_add_i32_e64 v1, s[4:5], -1, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s8, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_iszero_or_qnan_f16:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s8, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v1
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
|
|
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_iszero_or_qnan_f16:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39d
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_iszero_or_qnan_f16:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39d
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_iszero_or_qnan_f16:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39d
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_iszero_or_qnan_f16:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39d
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 925) ; ~(0x60|0x2) = "~(zero|qnan)"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @not_iszero_or_snan_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_iszero_or_snan_f16:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7dff
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_add_i32_e64 v1, s[4:5], -1, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s6, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
|
|
; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_iszero_or_snan_f16:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_iszero_or_snan_f16:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39e
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_iszero_or_snan_f16:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39e
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_iszero_or_snan_f16:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39e
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_iszero_or_snan_f16:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39e
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 926) ; ~(0x60|0x1) = "~(zero|snan)"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @isinf_or_nan_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: isinf_or_nan_f16:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7bff
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isinf_or_nan_f16:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: isinf_or_nan_f16:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x207
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: isinf_or_nan_f16:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x207
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: isinf_or_nan_f16:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x207
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: isinf_or_nan_f16:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x207
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 519) ; 0x204|0x3 = "inf|nan"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @not_isinf_or_nan_f16(half %x) {
|
|
; GFX7SELDAG-LABEL: not_isinf_or_nan_f16:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_isinf_or_nan_f16:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_isinf_or_nan_f16:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x1f8
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_isinf_or_nan_f16:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x1f8
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_isinf_or_nan_f16:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x1f8
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_isinf_or_nan_f16:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1f8
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 504) ; ~(0x204|0x3) = "~(inf|nan)"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @isfinite_or_nan_f(half %x) {
|
|
; GFX7SELDAG-LABEL: isfinite_or_nan_f:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: isfinite_or_nan_f:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
|
|
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0
|
|
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: isfinite_or_nan_f:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x1fb
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: isfinite_or_nan_f:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x1fb
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: isfinite_or_nan_f:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x1fb
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: isfinite_or_nan_f:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1fb
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 507) ; 0x1f8|0x3 = "finite|nan"
|
|
ret i1 %0
|
|
}
|
|
|
|
define i1 @not_isfinite_or_nan_f(half %x) {
|
|
; GFX7SELDAG-LABEL: not_isfinite_or_nan_f:
|
|
; GFX7SELDAG: ; %bb.0: ; %entry
|
|
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
|
|
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
|
|
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX7GLISEL-LABEL: not_isfinite_or_nan_f:
|
|
; GFX7GLISEL: ; %bb.0: ; %entry
|
|
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
|
|
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
|
|
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
|
|
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX8CHECK-LABEL: not_isfinite_or_nan_f:
|
|
; GFX8CHECK: ; %bb.0: ; %entry
|
|
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x204
|
|
; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9CHECK-LABEL: not_isfinite_or_nan_f:
|
|
; GFX9CHECK: ; %bb.0: ; %entry
|
|
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x204
|
|
; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
|
|
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
|
|
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX10CHECK-LABEL: not_isfinite_or_nan_f:
|
|
; GFX10CHECK: ; %bb.0: ; %entry
|
|
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x204
|
|
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11CHECK-LABEL: not_isfinite_or_nan_f:
|
|
; GFX11CHECK: ; %bb.0: ; %entry
|
|
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x204
|
|
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
entry:
|
|
%0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 516) ; ~(0x1f8|0x3) = "~(finite|nan)"
|
|
ret i1 %0
|
|
}
|
|
|
|
declare i1 @llvm.is.fpclass.f16(half, i32)
|
|
declare <2 x i1> @llvm.is.fpclass.v2f16(<2 x half>, i32)
|
|
declare <3 x i1> @llvm.is.fpclass.v3f16(<3 x half>, i32)
|
|
declare <4 x i1> @llvm.is.fpclass.v4f16(<4 x half>, i32)
|
|
|
|
; Assume DAZ
|
|
attributes #0 = { "denormal-fp-math"="ieee,preserve-sign" }
|
|
|
|
; Maybe daz
|
|
attributes #1 = { "denormal-fp-math"="ieee,dynamic" }
|