a496c8be6e
And dependent commits. Details in D150388. This reverts commit825b7f0ca5. This reverts commit7a98f084c4. This reverts commitb4a62b1fa5. This reverts commitb7836d8562. No conflicts in the code, few tests had conflicts in autogenerated CHECKs: llvm/test/CodeGen/Thumb2/mve-float32regloops.ll llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll Reviewed By: alexfh Differential Revision: https://reviews.llvm.org/D156381
108 lines
4.3 KiB
LLVM
108 lines
4.3 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc -verify-machineinstrs=0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=DEFAULT %s
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; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=greedy -vgpr-regalloc=greedy -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=DEFAULT %s
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; RUN: llc -verify-machineinstrs=0 -O0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=O0 %s
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; RUN: llc -verify-machineinstrs=0 -vgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=DEFAULT-BASIC %s
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; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=BASIC-DEFAULT %s
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; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=basic -vgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=BASIC-BASIC %s
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; RUN: not --crash llc -verify-machineinstrs=0 -regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=REGALLOC %s
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; RUN: not --crash llc -verify-machineinstrs=0 -regalloc=fast -O0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=REGALLOC %s
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; REGALLOC: -regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc
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; DEFAULT: Greedy Register Allocator
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; DEFAULT-NEXT: Virtual Register Rewriter
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; DEFAULT-NEXT: SI lower SGPR spill instructions
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; DEFAULT-NEXT: Virtual Register Map
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; DEFAULT-NEXT: Live Register Matrix
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; DEFAULT-NEXT: Greedy Register Allocator
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; DEFAULT-NEXT: GCN NSA Reassign
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; DEFAULT-NEXT: Virtual Register Rewriter
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; DEFAULT-NEXT: Stack Slot Coloring
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; O0: Fast Register Allocator
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; O0-NEXT: SI lower SGPR spill instructions
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; O0-NEXT: Fast Register Allocator
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; O0-NEXT: SI Fix VGPR copies
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; BASIC-DEFAULT: Debug Variable Analysis
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; BASIC-DEFAULT-NEXT: Live Stack Slot Analysis
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; BASIC-DEFAULT-NEXT: Machine Natural Loop Construction
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; BASIC-DEFAULT-NEXT: Machine Block Frequency Analysis
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; BASIC-DEFAULT-NEXT: Virtual Register Map
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; BASIC-DEFAULT-NEXT: Live Register Matrix
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; BASIC-DEFAULT-NEXT: Basic Register Allocator
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; BASIC-DEFAULT-NEXT: Virtual Register Rewriter
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; BASIC-DEFAULT-NEXT: SI lower SGPR spill instructions
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; BASIC-DEFAULT-NEXT: Virtual Register Map
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; BASIC-DEFAULT-NEXT: Live Register Matrix
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; BASIC-DEFAULT-NEXT: Bundle Machine CFG Edges
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; BASIC-DEFAULT-NEXT: Spill Code Placement Analysis
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; BASIC-DEFAULT-NEXT: Lazy Machine Block Frequency Analysis
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; BASIC-DEFAULT-NEXT: Machine Optimization Remark Emitter
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; BASIC-DEFAULT-NEXT: Greedy Register Allocator
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; BASIC-DEFAULT-NEXT: GCN NSA Reassign
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; BASIC-DEFAULT-NEXT: Virtual Register Rewriter
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; BASIC-DEFAULT-NEXT: Stack Slot Coloring
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; DEFAULT-BASIC: Greedy Register Allocator
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; DEFAULT-BASIC-NEXT: Virtual Register Rewriter
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; DEFAULT-BASIC-NEXT: SI lower SGPR spill instructions
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; DEFAULT-BASIC-NEXT: Virtual Register Map
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; DEFAULT-BASIC-NEXT: Live Register Matrix
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; DEFAULT-BASIC-NEXT: Basic Register Allocator
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; DEFAULT-BASIC-NEXT: GCN NSA Reassign
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; DEFAULT-BASIC-NEXT: Virtual Register Rewriter
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; DEFAULT-BASIC-NEXT: Stack Slot Coloring
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; BASIC-BASIC: Debug Variable Analysis
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; BASIC-BASIC-NEXT: Live Stack Slot Analysis
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; BASIC-BASIC-NEXT: Machine Natural Loop Construction
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; BASIC-BASIC-NEXT: Machine Block Frequency Analysis
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; BASIC-BASIC-NEXT: Virtual Register Map
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; BASIC-BASIC-NEXT: Live Register Matrix
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; BASIC-BASIC-NEXT: Basic Register Allocator
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; BASIC-BASIC-NEXT: Virtual Register Rewriter
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; BASIC-BASIC-NEXT: SI lower SGPR spill instructions
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; BASIC-BASIC-NEXT: Virtual Register Map
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; BASIC-BASIC-NEXT: Live Register Matrix
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; BASIC-BASIC-NEXT: Basic Register Allocator
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; BASIC-BASIC-NEXT: GCN NSA Reassign
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; BASIC-BASIC-NEXT: Virtual Register Rewriter
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; BASIC-BASIC-NEXT: Stack Slot Coloring
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declare void @bar()
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; Something with some CSR SGPR spills
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define void @foo() {
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call void asm sideeffect "; clobber", "~{s33}"()
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call void @bar()
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ret void
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}
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; Block live out spills with fast regalloc
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define amdgpu_kernel void @control_flow(i1 %cond) {
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%s33 = call i32 asm sideeffect "; clobber", "={s33}"()
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br i1 %cond, label %bb0, label %bb1
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bb0:
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call void asm sideeffect "; use %0", "s"(i32 %s33)
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br label %bb1
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bb1:
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ret void
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}
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