a496c8be6e
And dependent commits. Details in D150388. This reverts commit825b7f0ca5. This reverts commit7a98f084c4. This reverts commitb4a62b1fa5. This reverts commitb7836d8562. No conflicts in the code, few tests had conflicts in autogenerated CHECKs: llvm/test/CodeGen/Thumb2/mve-float32regloops.ll llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll Reviewed By: alexfh Differential Revision: https://reviews.llvm.org/D156381
71 lines
3.1 KiB
LLVM
71 lines
3.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SGPR %s
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; Make sure this doesn't crash.
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; ALL-LABEL: {{^}}test:
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; ALL: s_mov_b32 s[[LO:[0-9]+]], SCRATCH_RSRC_DWORD0
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; ALL: s_mov_b32 s[[HI:[0-9]+]], 0xe80000
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; Make sure we are handling hazards correctly.
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; SGPR: buffer_load_dword [[VHI:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:4
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; SGPR-NEXT: s_waitcnt vmcnt(0)
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; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 0
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; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 1
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; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 2
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; SGPR-NEXT: v_readlane_b32 s[[HI:[0-9]+]], [[VHI]], 3
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; SGPR-NEXT: buffer_load_dword [[VHI]], off, s[96:99], 0
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; SGPR-NEXT: s_waitcnt vmcnt(0)
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; SGPR-NEXT: s_mov_b64 exec, s[4:5]
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; SGPR-NEXT: s_nop 1
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; SGPR-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; ALL: s_endpgm
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define amdgpu_kernel void @test(ptr addrspace(1) %out, i32 %in) {
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call void asm sideeffect "", "~{s[0:7]}" ()
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call void asm sideeffect "", "~{s[8:15]}" ()
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call void asm sideeffect "", "~{s[16:23]}" ()
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call void asm sideeffect "", "~{s[24:31]}" ()
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call void asm sideeffect "", "~{s[32:39]}" ()
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call void asm sideeffect "", "~{s[40:47]}" ()
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call void asm sideeffect "", "~{s[48:55]}" ()
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call void asm sideeffect "", "~{s[56:63]}" ()
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call void asm sideeffect "", "~{s[64:71]}" ()
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call void asm sideeffect "", "~{s[72:79]}" ()
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call void asm sideeffect "", "~{s[80:87]}" ()
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call void asm sideeffect "", "~{s[88:95]}" ()
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call void asm sideeffect "", "~{v[0:7]}" ()
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call void asm sideeffect "", "~{v[8:15]}" ()
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call void asm sideeffect "", "~{v[16:23]}" ()
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call void asm sideeffect "", "~{v[24:31]}" ()
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call void asm sideeffect "", "~{v[32:39]}" ()
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call void asm sideeffect "", "~{v[40:47]}" ()
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call void asm sideeffect "", "~{v[48:55]}" ()
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call void asm sideeffect "", "~{v[56:63]}" ()
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call void asm sideeffect "", "~{v[64:71]}" ()
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call void asm sideeffect "", "~{v[72:79]}" ()
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call void asm sideeffect "", "~{v[80:87]}" ()
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call void asm sideeffect "", "~{v[88:95]}" ()
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call void asm sideeffect "", "~{v[96:103]}" ()
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call void asm sideeffect "", "~{v[104:111]}" ()
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call void asm sideeffect "", "~{v[112:119]}" ()
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call void asm sideeffect "", "~{v[120:127]}" ()
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call void asm sideeffect "", "~{v[128:135]}" ()
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call void asm sideeffect "", "~{v[136:143]}" ()
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call void asm sideeffect "", "~{v[144:151]}" ()
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call void asm sideeffect "", "~{v[152:159]}" ()
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call void asm sideeffect "", "~{v[160:167]}" ()
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call void asm sideeffect "", "~{v[168:175]}" ()
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call void asm sideeffect "", "~{v[176:183]}" ()
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call void asm sideeffect "", "~{v[184:191]}" ()
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call void asm sideeffect "", "~{v[192:199]}" ()
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call void asm sideeffect "", "~{v[200:207]}" ()
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call void asm sideeffect "", "~{v[208:215]}" ()
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call void asm sideeffect "", "~{v[216:223]}" ()
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call void asm sideeffect "", "~{v[224:231]}" ()
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call void asm sideeffect "", "~{v[232:239]}" ()
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call void asm sideeffect "", "~{v[240:247]}" ()
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call void asm sideeffect "", "~{v[248:255]}" ()
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store i32 %in, ptr addrspace(1) %out
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ret void
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}
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