1b12b1a335
The expansion of the various MOVi32imm pseudo-instructions works by splitting the operand into components (either halfwords or bytes) and emitting instructions to combine those components into the final result. When the operand is an immediate with some components being zero this can result in pointless instructions that just add zero. Avoid this by restructuring things so that a separate function handles splitting the operand into components, then don't emit the component if it is a zero immediate. This is straightforward for movw/movt, where we just don't emit the movt if it's zero, but the thumb1 expansion using mov/add/lsl is more complex, as even when we don't emit a given byte we still need to get the shift correct. Differential Revision: https://reviews.llvm.org/D154943
51 lines
1.6 KiB
LLVM
51 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
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; RUN: llc -mtriple=thumbv6m-eabi -mattr=+execute-only %s -o - -filetype=obj | \
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; RUN: llvm-objdump -d --no-leading-addr --no-show-raw-insn - | FileCheck %s
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define void @test1() {
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; CHECK-LABEL: <test1>:
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;; are we using correct prologue immediate materialization pattern for
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;; execute only
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; CHECK: sub sp, #0x100
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%tmp = alloca [ 64 x i32 ] , align 4
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ret void
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}
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define void @test2() {
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; CHECK-LABEL: <test2>:
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;; are we using correct prologue immediate materialization pattern for
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;; execute-only
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; CHECK: movs [[REG:r[0-9]+]], #0xff
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xff
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xef
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xb8
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%tmp = alloca [ 4168 x i8 ] , align 4
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ret void
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}
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define i32 @test3() {
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;; are we using correct prologue immediate materialization pattern for
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;; execute-only
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; CHECK-LABEL: <test3>:
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; CHECK: movs [[REG:r[0-9]+]], #0xcf
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xff
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xff
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xf0
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%retval = alloca i32, align 4
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%tmp = alloca i32, align 4
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%a = alloca [u0x30000001 x i8], align 16
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store i32 0, ptr %tmp
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;; are we choosing correct store/tSTRspi pattern for execute-only
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; CHECK: movs [[REG:r[0-9]+]], #0x30
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x18
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; CHECK-NEXT: adds [[REG]], #0x8
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%tmp1 = load i32, ptr %tmp
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ret i32 %tmp1
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}
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