d4ce862f2a
We currently have strict floating point/constrained floating point enabled for all targets. Constrained SDAG nodes get converted to the regular ones before reaching the target layer. In theory this should be fine. However, the changes are exposed to users through multiple clang options already in use in the field, and the changes are _completely_ _untested_ on almost all of our targets. Bugs have already been found, like "https://bugs.llvm.org/show_bug.cgi?id=45274". This patch disables constrained floating point options in clang everywhere except X86 and SystemZ. A warning will be printed when this happens. Use the new -fexperimental-strict-floating-point flag to force allowing strict floating point on hosts that aren't already marked as supporting it (X86 and SystemZ). Differential Revision: https://reviews.llvm.org/D80952
63 lines
3.3 KiB
C
63 lines
3.3 KiB
C
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
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// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm -o - %s \
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// RUN: | opt -S -mem2reg | FileCheck --check-prefix=COMMON --check-prefix=COMMONIR --check-prefix=UNCONSTRAINED %s
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// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
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// RUN: -ffp-exception-behavior=strict \
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// RUN: -fexperimental-strict-floating-point \
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// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm -o - %s \
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// RUN: | opt -S -mem2reg | FileCheck --check-prefix=COMMON --check-prefix=COMMONIR --check-prefix=CONSTRAINED %s
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// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
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// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -S -o - %s \
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// RUN: | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM %s
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// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
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// RUN: -ffp-exception-behavior=strict \
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// RUN: -fexperimental-strict-floating-point \
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// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -S -o - %s \
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// RUN: | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM %s
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// REQUIRES: aarch64-registered-target
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// Test new aarch64 intrinsics and types but constrained
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#include <arm_neon.h>
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// COMMON-LABEL: test_vrndaq_f64
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// COMMONIR: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
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// UNCONSTRAINED: [[VRNDA1_I:%.*]] = call <2 x double> @llvm.round.v2f64(<2 x double> %a)
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// CONSTRAINED: [[VRNDA1_I:%.*]] = call <2 x double> @llvm.experimental.constrained.round.v2f64(<2 x double> %a, metadata !"fpexcept.strict")
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// CHECK-ASM: frinta v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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// COMMONIR: ret <2 x double> [[VRNDA1_I]]
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float64x2_t test_vrndaq_f64(float64x2_t a) {
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return vrndaq_f64(a);
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}
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// COMMON-LABEL: test_vrndpq_f64
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// COMMONIR: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
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// UNCONSTRAINED: [[VRNDP1_I:%.*]] = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a)
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// CONSTRAINED: [[VRNDP1_I:%.*]] = call <2 x double> @llvm.experimental.constrained.ceil.v2f64(<2 x double> %a, metadata !"fpexcept.strict")
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// CHECK-ASM: frintp v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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// COMMONIR: ret <2 x double> [[VRNDP1_I]]
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float64x2_t test_vrndpq_f64(float64x2_t a) {
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return vrndpq_f64(a);
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}
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// COMMON-LABEL: test_vsqrtq_f32
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// COMMONIR: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
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// UNCONSTRAINED: [[VSQRT_I:%.*]] = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
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// CONSTRAINED: [[VSQRT_I:%.*]] = call <4 x float> @llvm.experimental.constrained.sqrt.v4f32(<4 x float> %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
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// CHECK-ASM: fsqrt v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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// COMMONIR: ret <4 x float> [[VSQRT_I]]
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float32x4_t test_vsqrtq_f32(float32x4_t a) {
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return vsqrtq_f32(a);
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}
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// COMMON-LABEL: test_vsqrtq_f64
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// COMMONIR: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
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// UNCONSTRAINED: [[VSQRT_I:%.*]] = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a)
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// CONSTRAINED: [[VSQRT_I:%.*]] = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double> %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
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// CHECK-ASM: fsqrt v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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// COMMONIR: ret <2 x double> [[VSQRT_I]]
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float64x2_t test_vsqrtq_f64(float64x2_t a) {
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return vsqrtq_f64(a);
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}
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