af64948e2a
Summary: Adds the constraints described below to ensure that we can tie variables of SVE ACLE types to operands in inline-asm: - y: SVE registers Z0-Z7 - Upl: One of the low eight SVE predicate registers (P0-P7) - Upa: Full range of SVE predicate registers (P0-P15) Reviewers: sdesmalen, huntergr, rovka, cameron.mcinally, efriedma, rengolin Reviewed By: efriedma Subscribers: miyuki, tschuett, rkruppe, psnobl, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D75690
25 lines
770 B
C
25 lines
770 B
C
// REQUIRES: aarch64-registered-target
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// RUN: not %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns \
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// RUN: -target-feature +neon -S -O1 -o - %s 2>&1 | FileCheck %s
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// Set a vector constraint for an sve predicate register
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// As the wrong constraint is used for an SVBool,
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// the compiler will try to extend the nxv16i1 to an nxv16i8
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// TODO: We don't have patterns for this yet but once they are added this test
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// should be updated to check for an assembler error
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__SVBool_t funcB1(__SVBool_t in)
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{
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__SVBool_t ret ;
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asm volatile (
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"mov %[ret].b, %[in].b \n"
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: [ret] "=w" (ret)
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: [in] "w" (in)
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:);
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return ret ;
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}
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// CHECK: funcB1
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// CHECK-ERROR: fatal error: error in backend: Cannot select
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