28b172e341
The R_ARM_ALU_PC_G0 and R_ARM_LDR_PC_G0 relocations are used by the ADR and LDR pseudo instructions, and are the basis of the group relocations that can load an arbitrary constant via a series of add, sub and ldr instructions. The relocations need to be obtained via the .reloc directive. R_ARM_ALU_PC_G0 is much more complicated as the add/sub instruction uses a modified immediate encoding of an 8-bit immediate rotated right by an even 4-bit field. This means that the range of representable immediates is sparse. We extract the encoding and decoding functions for the modified immediate from llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h as this header file is not accessible from LLD. Duplication of code isn't ideal, but as these are well-defined mathematical functions they are unlikely to change. Differential Revision: https://reviews.llvm.org/D75349
31 lines
837 B
ArmAsm
31 lines
837 B
ArmAsm
// REQUIRES: arm
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// RUN: llvm-mc --triple=armv7a-none-eabi --arm-add-build-attributes -filetype=obj -o %t.o %s
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// RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck %s
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.section .os0, "ax", %progbits
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.balign 1024
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.thumb_func
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low:
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bx lr
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/// Check that we error when the immediate for the add or sub is not encodeable
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.section .os1, "ax", %progbits
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.arm
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.balign 1024
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.global _start
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.type _start, %function
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_start:
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// CHECK: {{.*}}.s.tmp.o:(.os1+0x0): unencodeable immediate 1031 for relocation R_ARM_ALU_PC_G0
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/// adr r0, low
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.inst 0xe24f0008
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.reloc 0, R_ARM_ALU_PC_G0, low
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// CHECK: {{.*}}.s.tmp.o:(.os1+0x4): unencodeable immediate 1013 for relocation R_ARM_ALU_PC_G0
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/// adr r1, unaligned
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.inst 0xe24f1008
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.reloc 4, R_ARM_ALU_PC_G0, unaligned
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.section .os2, "ax", %progbits
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.balign 1024
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.thumb_func
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unaligned:
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bx lr
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