b257d3c8a8
The current implementation assumes that R_PPC64_TOC16_HA is always followed by R_PPC64_TOC16_LO_DS. This can break with R_PPC64_TOC16_LO: // Load the address of the TOC entry, instead of the value stored at that address addis 3, 2, .LC0@tloc@ha # R_PPC64_TOC16_HA addi 3, 3, .LC0@tloc@l # R_PPC64_TOC16_LO blr which is used by boringssl's util/fipstools/delocate/delocate.go https://github.com/google/boringssl/blob/master/crypto/fipsmodule/FIPS.md has some documentation. In short, this tool converts an assembly file to avoid any potential relocations. The distance to an input .toc is not a constant after linking, so it cannot use an `addis;ld` pair. Instead, it jumps to a stub which loads the TOC entry address with `addis;addi`. This patch checks the presence of R_PPC64_TOC16_LO and suppresses toc-indirect to toc-relative relaxation if R_PPC64_TOC16_LO is seen. This approach is conservative and loses some relaxation opportunities but is easy to implement. addis 3, 2, .LC0@toc@ha # no relaxation addi 3, 3, .LC0@toc@l # no relaxation li 9, 0 addis 4, 2, .LC0@toc@ha # can relax but suppressed ld 4, .LC0@toc@l(4) # can relax but suppressed Also note that interleaved R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS is possible and this patch accounts for that. addis 3, 2, .LC1@toc@ha # can relax addis 4, 2, .LC2@toc@ha # can relax ld 3, .LC1@toc@l(3) # can relax ld 4, .LC2@toc@l(4) # can relax Reviewed By: #powerpc, sfertile Differential Revision: https://reviews.llvm.org/D78431
67 lines
1.9 KiB
ArmAsm
67 lines
1.9 KiB
ArmAsm
# REQUIRES: ppc
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# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s -o %t.o
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# RUN: echo 'addis 5, 2, .LC0@toc@ha; ld 5, .LC0@toc@l(5); foo: \
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# RUN: .section .toc,"aw",@progbits; .LC0: .tc foo[TC], foo' \
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# RUN: | llvm-mc -filetype=obj -triple=powerpc64le - -o %t1.o
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# RUN: ld.lld %t.o %t1.o -o %t
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# RUN: llvm-objdump -d %t | FileCheck %s
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# CHECK-LABEL: <_start>:
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.globl _start
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_start:
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## Perform toc-indirect to toc-relative relaxation even if there are unrelated instructions in between.
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# CHECK-NEXT: addis 3, 2, -2
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# CHECK-NEXT: li 9, 0
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# CHECK-NEXT: addi 3, 3, 32752
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# CHECK-NEXT: lwa 3, 0(3)
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addis 3, 2, .LC1@toc@ha # R_PPC64_TOC16_HA
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li 9, 0
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ld 3, .LC1@toc@l(3) # R_PPC64_TOC16_LO_DS
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lwa 3, 0(3)
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## R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS can interleave.
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# CHECK-NEXT: addis 3, 2, -2
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# CHECK-NEXT: addis 4, 2, -2
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# CHECK-NEXT: addi 3, 3, 32752
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# CHECK-NEXT: addi 4, 4, 32756
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addis 3, 2, .LC1@toc@ha
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addis 4, 2, .LC2@toc@ha
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ld 3, .LC1@toc@l(3)
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ld 4, .LC2@toc@l(4)
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## We choose to be conservative: the presence of R_PPC64_TOC16_LO
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## suppresses relaxation for the symbol.
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## R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS pairs are not relaxed as well.
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# CHECK-NEXT: nop
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# CHECK-NEXT: addi 3, 2, -32768
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# CHECK-NEXT: li 9, 0
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# CHECK-NEXT: nop
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# CHECK-NEXT: ld 4, -32768(2)
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addis 3, 2, .LC0@toc@ha # R_PPC64_TOC16_HA
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addi 3, 3, .LC0@toc@l # R_PPC64_TOC16_LO
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li 9, 0
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addis 4, 2, .LC0@toc@ha
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ld 4, .LC0@toc@l(4)
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# CHECK-COUNT-3: blr
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AES_encrypt:
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blr
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AES_decrypt:
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blr
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BN_free:
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blr
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## %t1.o has relaxable relocation pairs referencing its .toc which is different
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## from %t.o(.toc). The suppression in %t.o does not affect %t1.o even if
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## the relocation addends are the same.
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# CHECK-NEXT: addis 5, 2, -1
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# CHECK-NEXT: addi 5, 5, -32768
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.section .toc,"aw",@progbits
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.LC0:
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.tc AES_encrypt[TC], AES_encrypt
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.LC1:
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.tc AES_decrypt[TC], AES_decrypt
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.LC2:
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.tc BN_free[TC], BN_free
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