387d3c2479
MCTargetDesc includes headers from Utils and Utils includes headers from MCTargetDesc. So from a library layering perspective it makes sense for them to be in the same library. I guess the other option might be to move the tablegen includes from RISCVMCTargetDesc.h to RISCVBaseInfo.h so that RISCVBaseInfo.h didn't need to include RISCVMCTargetDesc.h. Everything else that depends on Utils also depends on MCTargetDesc so having one library seemed simpler. Differential Revision: https://reviews.llvm.org/D93168
119 lines
4.6 KiB
C++
119 lines
4.6 KiB
C++
//===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVFixupKinds.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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namespace llvm {
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class MCAssembler;
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class MCObjectTargetWriter;
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class raw_ostream;
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class RISCVAsmBackend : public MCAsmBackend {
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const MCSubtargetInfo &STI;
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uint8_t OSABI;
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bool Is64Bit;
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bool ForceRelocs = false;
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const MCTargetOptions &TargetOptions;
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RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
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public:
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RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
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const MCTargetOptions &Options)
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: MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
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TargetOptions(Options) {
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TargetABI = RISCVABI::computeTargetABI(
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STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName());
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RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
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}
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~RISCVAsmBackend() override {}
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void setForceRelocs() { ForceRelocs = true; }
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// Returns true if relocations will be forced for shouldForceRelocation by
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// default. This will be true if relaxation is enabled or had previously
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// been enabled.
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bool willForceRelocations() const {
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return ForceRelocs || STI.getFeatureBits()[RISCV::FeatureRelax];
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}
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// Generate diff expression relocations if the relax feature is enabled or had
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// previously been enabled, otherwise it is safe for the assembler to
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// calculate these internally.
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bool requiresDiffExpressionRelocations() const override {
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return willForceRelocations();
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}
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// Return Size with extra Nop Bytes for alignment directive in code section.
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bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF,
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unsigned &Size) override;
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// Insert target specific fixup type for alignment directive in code section.
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bool shouldInsertFixupForCodeAlign(MCAssembler &Asm,
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const MCAsmLayout &Layout,
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MCAlignFragment &AF) override;
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bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout,
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const MCFixup &Fixup, const MCFragment *DF,
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const MCValue &Target, uint64_t &Value,
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bool &WasForced) override;
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void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, MutableArrayRef<char> Data,
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uint64_t Value, bool IsResolved,
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const MCSubtargetInfo *STI) const override;
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std::unique_ptr<MCObjectTargetWriter>
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createObjectTargetWriter() const override;
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bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target) override;
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
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}
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bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout,
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const bool WasForced) const override;
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unsigned getNumFixupKinds() const override {
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return RISCV::NumTargetFixupKinds;
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}
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Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
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bool mayNeedRelaxation(const MCInst &Inst,
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const MCSubtargetInfo &STI) const override;
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unsigned getRelaxedOpcode(unsigned Op) const;
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void relaxInstruction(MCInst &Inst,
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const MCSubtargetInfo &STI) const override;
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bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
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const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
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RISCVABI::ABI getTargetABI() const { return TargetABI; }
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};
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}
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#endif
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