19dc9c9780
Move the code which adjusts the immediate/predicate on a G_ICMP to AArch64PostLegalizerLowering. This - Reduces the number of places we need to test for optimized compares in the selector. We know that the compare should have been simplified by the time it hits the selector, so we can avoid testing this in selects, brconds, etc. - Allows us to potentially fold more compares (previously, this optimization was only done after calling `tryFoldCompare`, this may allow us to hit some more TST cases) - Simplifies the selection code in `emitIntegerCompare` significantly; we can just use an emitSUBS function. - Allows us to avoid checking that the predicate has been updated after `emitIntegerCompare`. Also add a utility header file for things that may be useful in the selector and various combiners. No need for an implementation file at this point, since it's just one constexpr function for now. I've run into a couple cases where having one of these would be handy, so might as well add it here. There are a couple functions in the selector that can probably be factored out into here. Differential Revision: https://reviews.llvm.org/D89823
188 lines
4.4 KiB
YAML
188 lines
4.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: cbz_s32
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: cbz_s32
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: CBZW [[COPY]], %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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bb.0:
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liveins: $w0
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successors: %bb.0, %bb.1
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = G_CONSTANT i32 0
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%2:gpr(s32) = G_ICMP intpred(eq), %0, %1
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%3:gpr(s1) = G_TRUNC %2(s32)
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G_BRCOND %3(s1), %bb.1
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G_BR %bb.0
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bb.1:
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...
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---
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name: cbz_s64
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: cbz_s64
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: CBZX [[COPY]], %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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bb.0:
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liveins: $x0
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successors: %bb.0, %bb.1
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 0
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%2:gpr(s32) = G_ICMP intpred(eq), %0, %1
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%3:gpr(s1) = G_TRUNC %2(s32)
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G_BRCOND %3(s1), %bb.1
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G_BR %bb.0
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bb.1:
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...
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---
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name: cbnz_s32
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: cbnz_s32
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: CBNZW [[COPY]], %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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bb.0:
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liveins: $w0
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successors: %bb.0, %bb.1
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = G_CONSTANT i32 0
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%2:gpr(s32) = G_ICMP intpred(ne), %0, %1
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%3:gpr(s1) = G_TRUNC %2(s32)
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G_BRCOND %3(s1), %bb.1
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G_BR %bb.0
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bb.1:
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...
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---
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name: cbnz_s64
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: cbnz_s64
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: CBNZX [[COPY]], %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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bb.0:
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liveins: $x0
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successors: %bb.0, %bb.1
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 0
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%2:gpr(s32) = G_ICMP intpred(ne), %0, %1
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%3:gpr(s1) = G_TRUNC %2(s32)
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G_BRCOND %3(s1), %bb.1
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G_BR %bb.0
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bb.1:
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...
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---
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name: test_rhs_inttoptr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: test_rhs_inttoptr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK: CBZX [[COPY]], %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: STRXui $xzr, [[COPY]], 0 :: (store 8)
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; CHECK: bb.2:
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; CHECK: RET_ReallyLR
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bb.1:
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successors: %bb.2, %bb.3
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liveins: $x0
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%0:gpr(p0) = COPY $x0
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%2:gpr(s64) = G_CONSTANT i64 0
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%1:gpr(p0) = G_INTTOPTR %2(s64)
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%4:gpr(s32) = G_ICMP intpred(eq), %0(p0), %1
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%3:gpr(s1) = G_TRUNC %4(s32)
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G_BRCOND %3(s1), %bb.3
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bb.2:
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%5:gpr(s64) = G_CONSTANT i64 0
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G_STORE %5(s64), %0(p0) :: (store 8)
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bb.3:
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RET_ReallyLR
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...
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---
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name: test_rhs_unknown
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: test_rhs_unknown
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui [[COPY]], 0 :: (load 8)
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; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[LDRXui]], 42, 0, implicit-def $nzcv
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; CHECK: Bcc 0, %bb.2, implicit $nzcv
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: STRXui $xzr, [[COPY]], 0 :: (store 8)
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; CHECK: bb.2:
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; CHECK: RET_ReallyLR
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bb.1:
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successors: %bb.2, %bb.3
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liveins: $x0
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%0:gpr(p0) = COPY $x0
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%2:gpr(s64) = G_CONSTANT i64 42
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%4:gpr(s64) = G_CONSTANT i64 0
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%1:gpr(s64) = G_LOAD %0(p0) :: (load 8)
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%5:gpr(s32) = G_ICMP intpred(eq), %1(s64), %2
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%3:gpr(s1) = G_TRUNC %5(s32)
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G_BRCOND %3(s1), %bb.3
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bb.2:
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%6:gpr(s64) = G_CONSTANT i64 0
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G_STORE %6(s64), %0(p0) :: (store 8)
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bb.3:
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RET_ReallyLR
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