c42053f79b
The manual selection code for add/sub was not checking if it was possible to fold in shifts + extends (the *rx opcode variants). As a result, we could never select things like ``` cmp x1, w0, uxtw #2 ``` Because we don't import any patterns for compares. This adds support for the arithmetic shifted register forms and updates tests for instructions selected using `emitADD`, `emitADDS`, and `emitSUBS`. This is a 0.1% geomean code size improvement on SPECINT2000 at -Os. Differential Revision: https://reviews.llvm.org/D91207
167 lines
5.3 KiB
YAML
167 lines
5.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-uknown -global-isel -run-pass=instruction-select %s -o - | FileCheck %s
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...
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---
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name: uaddo_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w0, $w1, $x2
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; CHECK-LABEL: name: uaddo_s32
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
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; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
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; CHECK: $w0 = COPY [[UBFMWri1]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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%3:gpr(s32), %4:gpr(s1) = G_UADDO %0, %1
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%5:gpr(s8) = G_ZEXT %4(s1)
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%6:gpr(s32) = G_ZEXT %5(s8)
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$w0 = COPY %6(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddo_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: uaddo_s64
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
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; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
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; CHECK: $w0 = COPY [[UBFMWri1]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = COPY $x1
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%3:gpr(s64), %4:gpr(s1) = G_UADDO %0, %1
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%5:gpr(s8) = G_ZEXT %4(s1)
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%6:gpr(s32) = G_ZEXT %5(s8)
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$w0 = COPY %6(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddo_s32_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w0, $w1, $x2
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; Check that we get ADDSWri when we can fold in a constant.
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;
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; CHECK-LABEL: name: uaddo_s32_imm
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: %copy:gpr32sp = COPY $w0
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; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
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; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
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; CHECK: $w0 = COPY %add
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; CHECK: RET_ReallyLR implicit $w0
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%copy:gpr(s32) = COPY $w0
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%constant:gpr(s32) = G_CONSTANT i32 16
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%add:gpr(s32), %overflow:gpr(s1) = G_UADDO %copy, %constant
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$w0 = COPY %add(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddo_s32_shifted
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w0, $w1, $x2
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; Check that we get ADDSWrs when we can fold in a shift.
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;
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; CHECK-LABEL: name: uaddo_s32_shifted
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: %copy1:gpr32 = COPY $w0
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; CHECK: %copy2:gpr32 = COPY $w1
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; CHECK: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
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; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
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; CHECK: $w0 = COPY %add
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; CHECK: RET_ReallyLR implicit $w0
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%copy1:gpr(s32) = COPY $w0
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%copy2:gpr(s32) = COPY $w1
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%constant:gpr(s32) = G_CONSTANT i32 16
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%shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
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%add:gpr(s32), %overflow:gpr(s1) = G_UADDO %copy1, %shift
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$w0 = COPY %add(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddo_s32_neg_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w0, $w1, $x2
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; Check that we get SUBSWri when we can fold in a negative constant.
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;
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; CHECK-LABEL: name: uaddo_s32_neg_imm
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: %copy:gpr32sp = COPY $w0
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; CHECK: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
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; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
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; CHECK: $w0 = COPY %add
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; CHECK: RET_ReallyLR implicit $w0
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%copy:gpr(s32) = COPY $w0
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%constant:gpr(s32) = G_CONSTANT i32 -16
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%add:gpr(s32), %overflow:gpr(s1) = G_UADDO %copy, %constant
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$w0 = COPY %add(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddo_arith_extended
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w0, $x0
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; Check that we get ADDSXrx.
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; CHECK-LABEL: name: uaddo_arith_extended
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; CHECK: liveins: $w0, $x0
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; CHECK: %reg0:gpr64sp = COPY $x0
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; CHECK: %reg1:gpr32 = COPY $w0
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; CHECK: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
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; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
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; CHECK: $x0 = COPY %add
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; CHECK: RET_ReallyLR implicit $x0
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%reg0:gpr(s64) = COPY $x0
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%reg1:gpr(s32) = COPY $w0
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%ext:gpr(s64) = G_ZEXT %reg1(s32)
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%cst:gpr(s64) = G_CONSTANT i64 2
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%shift:gpr(s64) = G_SHL %ext, %cst(s64)
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%add:gpr(s64), %flags:gpr(s1) = G_UADDO %reg0, %shift
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$x0 = COPY %add(s64)
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RET_ReallyLR implicit $x0
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