a88c722e68
PAC/BTI-related codegen in the AArch64 backend is controlled by a set of LLVM IR function attributes, added to the function by Clang, based on command-line options and GCC-style function attributes. However, functions, generated in the LLVM middle end (for example, asan.module.ctor or __llvm_gcov_write_out) do not get any attributes and the backend incorrectly does not do any PAC/BTI code generation. This patch record the default state of PAC/BTI codegen in a set of LLVM IR module-level attributes, based on command-line options: * "sign-return-address", with non-zero value means generate code to sign return addresses (PAC-RET), zero value means disable PAC-RET. * "sign-return-address-all", with non-zero value means enable PAC-RET for all functions, zero value means enable PAC-RET only for functions, which spill LR. * "sign-return-address-with-bkey", with non-zero value means use B-key for signing, zero value mean use A-key. This set of attributes are always added for AArch64 targets (as opposed, for example, to interpreting a missing attribute as having a value 0) in order to be able to check for conflicts when combining module attributed during LTO. Module-level attributes are overridden by function level attributes. All the decision making about whether to not to generate PAC and/or BTI code is factored out into AArch64FunctionInfo, there shouldn't be any places left, other than AArch64FunctionInfo, which directly examine PAC/BTI attributes, except AArch64AsmPrinter.cpp, which is/will-be handled by a separate patch. Differential Revision: https://reviews.llvm.org/D85649
45 lines
1.7 KiB
YAML
45 lines
1.7 KiB
YAML
# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
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# AArch64 Branch Target Enforcement treats the BR and BLR indirect branch
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# instructions differently. The BLR instruction can only target a BTI C
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# instruction, and the BR instruction can only target a BTI J instruction. We
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# always start indirectly-called functions with BTI C, so the outliner must not
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# transform a BLR instruction into a BR instruction.
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# There is an exception to this: BR X16 and BR X17 can also target a BTI C
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# instruction. We make of this for general tail-calls (tested elsewhere), but
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# don't currently make use of this in the outliner.
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# CHECK-NOT: OUTLINED_FUNCTION_
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--- |
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@g = hidden local_unnamed_addr global i32 0, align 4
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define hidden void @bar(void ()* nocapture %f) "branch-target-enforcement"="true" {
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entry:
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ret void
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}
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declare void @foo()
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...
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---
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name: bar
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x20, $x21, $lr, $x19
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HINT 34
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STRWui renamable $w21, renamable $x20, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g)
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BLR renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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STRWui renamable $w21, renamable $x20, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g)
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BLR renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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STRWui killed renamable $w21, killed renamable $x20, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g)
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BLR killed renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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TCRETURNdi @foo, 0, csr_aarch64_aapcs, implicit $sp
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...
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