314e29ed2b
Previously, instructions which could be expressed as VOP3 in addition to another encoding had a _e64 suffix on the tablegen record name, while those only available as VOP3 did not. With this patch, all VOP3s will have the _e64 suffix. The assembly does not change, only the mir. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D94341 Change-Id: Ia8ec8890d47f8f94bbbdac43745b4e9dd2b03423
129 lines
4.6 KiB
YAML
129 lines
4.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
|
|
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
|
|
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
|
|
|
|
# Note: 16-bit instructions generally produce a 0 result in the high 16-bits on GFX8 and GFX9 and preserve high 16 bits on GFX10+
|
|
|
|
---
|
|
name: add_s16
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $vgpr1
|
|
|
|
; GFX6-LABEL: name: add_s16
|
|
; GFX6: liveins: $vgpr0, $vgpr1
|
|
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
|
|
; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
|
|
; GFX10-LABEL: name: add_s16
|
|
; GFX10: liveins: $vgpr0, $vgpr1
|
|
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
|
|
; GFX10: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:vgpr(s32) = COPY $vgpr1
|
|
%2:vgpr(s16) = G_TRUNC %0
|
|
%3:vgpr(s16) = G_TRUNC %1
|
|
%4:vgpr(s16) = G_ADD %2, %3
|
|
S_ENDPGM 0, implicit %4
|
|
|
|
...
|
|
|
|
---
|
|
name: add_s16_zext_to_s32
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $vgpr1
|
|
|
|
; GFX6-LABEL: name: add_s16_zext_to_s32
|
|
; GFX6: liveins: $vgpr0, $vgpr1
|
|
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
|
|
; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
|
|
; GFX10-LABEL: name: add_s16_zext_to_s32
|
|
; GFX10: liveins: $vgpr0, $vgpr1
|
|
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
|
|
; GFX10: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[V_ADD_U16_e64_]], 0, 16, implicit $exec
|
|
; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:vgpr(s32) = COPY $vgpr1
|
|
%2:vgpr(s16) = G_TRUNC %0
|
|
%3:vgpr(s16) = G_TRUNC %1
|
|
%4:vgpr(s16) = G_ADD %2, %3
|
|
%5:vgpr(s32) = G_ZEXT %4
|
|
S_ENDPGM 0, implicit %5
|
|
|
|
...
|
|
|
|
---
|
|
name: add_s16_neg_inline_const_64
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
|
|
; GFX6-LABEL: name: add_s16_neg_inline_const_64
|
|
; GFX6: liveins: $vgpr0
|
|
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
|
|
; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
|
|
; GFX10-LABEL: name: add_s16_neg_inline_const_64
|
|
; GFX10: liveins: $vgpr0
|
|
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
|
|
; GFX10: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:vgpr(s16) = G_TRUNC %0
|
|
%2:vgpr(s16) = G_CONSTANT i16 -64
|
|
%3:vgpr(s16) = G_ADD %1, %2
|
|
S_ENDPGM 0, implicit %3
|
|
|
|
...
|
|
|
|
---
|
|
name: add_s16_neg_inline_const_64_zext_to_s32
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
|
|
; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
|
|
; GFX6: liveins: $vgpr0
|
|
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
|
|
; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
|
|
; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
|
|
; GFX10: liveins: $vgpr0
|
|
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
|
|
; GFX10: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[V_SUB_U16_e64_]], 0, 16, implicit $exec
|
|
; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:vgpr(s16) = G_TRUNC %0
|
|
%2:vgpr(s16) = G_CONSTANT i16 -64
|
|
%3:vgpr(s16) = G_ADD %1, %2
|
|
%4:vgpr(s32) = G_ZEXT %3
|
|
S_ENDPGM 0, implicit %4
|
|
|
|
...
|