2291bd137d
Support for XNACK and SRAMECC is not static on some GPUs. We must be able to differentiate between different scenarios for these dynamic subtarget features. The possible settings are: - Unsupported: The GPU has no support for XNACK/SRAMECC. - Any: Preference is unspecified. Use conservative settings that can run anywhere. - Off: Request support for XNACK/SRAMECC Off - On: Request support for XNACK/SRAMECC On GCNSubtarget will track the four options based on the following criteria. If the subtarget does not support XNACK/SRAMECC we say the setting is "Unsupported". If no subtarget features for XNACK/SRAMECC are requested we must support "Any" mode. If the subtarget features XNACK/SRAMECC exist in the feature string when initializing the subtarget, the settings are "On/Off". The defaults are updated to be conservatively correct, meaning if no setting for XNACK or SRAMECC is explicitly requested, defaults will be used which generate code that can be run anywhere. This corresponds to the "Any" setting. Differential Revision: https://reviews.llvm.org/D85882
74 lines
3.3 KiB
LLVM
74 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: opt -S -codegenprepare -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=GCN %s
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; Make sure we match the addressing mode offset of globla.atomic.fadd intrinsics across blocks.
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define amdgpu_kernel void @test_sink_small_offset_global_atomic_fadd_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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; OPT-LABEL: @test_sink_small_offset_global_atomic_fadd_f32(
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; OPT-NEXT: entry:
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; OPT-NEXT: [[OUT_GEP:%.*]] = getelementptr float, float addrspace(1)* [[OUT:%.*]], i32 999999
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; OPT-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) [[ATTR3:#.*]]
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; OPT-NEXT: [[CMP:%.*]] = icmp eq i32 [[TID]], 0
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; OPT-NEXT: br i1 [[CMP]], label [[ENDIF:%.*]], label [[IF:%.*]]
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; OPT: if:
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; OPT-NEXT: [[TMP0:%.*]] = bitcast float addrspace(1)* [[IN:%.*]] to i8 addrspace(1)*
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; OPT-NEXT: [[SUNKADDR:%.*]] = getelementptr i8, i8 addrspace(1)* [[TMP0]], i64 28
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; OPT-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(1)* [[SUNKADDR]] to float addrspace(1)*
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; OPT-NEXT: [[FADD2:%.*]] = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* [[TMP1]], float 2.000000e+00)
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; OPT-NEXT: [[VAL:%.*]] = load volatile float, float addrspace(1)* undef, align 4
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; OPT-NEXT: br label [[ENDIF]]
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; OPT: endif:
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; OPT-NEXT: [[X:%.*]] = phi float [ [[VAL]], [[IF]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
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; OPT-NEXT: store float [[X]], float addrspace(1)* [[OUT_GEP]], align 4
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; OPT-NEXT: ret void
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;
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; GCN-LABEL: test_sink_small_offset_global_atomic_fadd_f32:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; GCN-NEXT: s_cbranch_execz BB0_2
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; GCN-NEXT: ; %bb.1: ; %if
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: v_mov_b32_e32 v1, 2.0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_atomic_add_f32 v0, v1, s[2:3] offset:28
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; GCN-NEXT: global_load_dword v0, v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: BB0_2: ; %endif
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; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
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; GCN-NEXT: v_mov_b32_e32 v1, 0x3d0000
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_store_dword v1, v0, s[0:1] offset:2300
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; GCN-NEXT: s_endpgm
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entry:
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 999999
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%in.gep = getelementptr float, float addrspace(1)* %in, i32 7
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%cmp = icmp eq i32 %tid, 0
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br i1 %cmp, label %endif, label %if
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if:
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%fadd2 = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %in.gep, float 2.0)
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%val = load volatile float, float addrspace(1)* undef
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br label %endif
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endif:
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%x = phi float [ %val, %if ], [ 0.0, %entry ]
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store float %x, float addrspace(1)* %out.gep
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br label %done
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done:
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ret void
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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declare float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* nocapture, float) #2
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attributes #0 = { argmemonly nounwind }
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attributes #1 = { nounwind readnone willreturn }
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attributes #2 = { argmemonly nounwind willreturn }
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