d91a9e27a9
This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
21 lines
902 B
LLVM
21 lines
902 B
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; This code causes any_extend_vector_inreg to appear in the selection DAG.
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; Make sure that it is handled instead of crashing.
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; CHECK: vmem
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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define fastcc void @fred(i16* %a0, <16 x i32>* %a1) #0 {
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b0:
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%v1 = load i16, i16* %a0, align 2
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%v2 = insertelement <16 x i16> undef, i16 %v1, i32 15
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%v3 = zext <16 x i16> %v2 to <16 x i32>
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%v4 = shl nuw <16 x i32> %v3, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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store <16 x i32> %v4, <16 x i32>* %a1, align 4
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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