d91a9e27a9
This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
42 lines
1.8 KiB
LLVM
42 lines
1.8 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; During lowering, a BUILD_VECTOR of undef values was created. This was
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; not properly handled by buildHvxVectorReg, which tried to generate a
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; splat, but had no source value.
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;
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; Check that this compiles successfully.
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; CHECK: vsplat
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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@g0 = global <32 x i8> zeroinitializer
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define void @fred(i8* %a0) #0 {
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b0:
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%v1 = load i8, i8* %a0, align 1
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%v2 = insertelement <32 x i8> undef, i8 %v1, i32 31
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%v3 = zext <32 x i8> %v2 to <32 x i16>
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%v4 = add nuw nsw <32 x i16> %v3, zeroinitializer
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%v5 = add nuw nsw <32 x i16> %v4, zeroinitializer
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%v6 = add nuw nsw <32 x i16> %v5, zeroinitializer
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%v7 = add nuw nsw <32 x i16> %v6, zeroinitializer
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%v8 = add nuw nsw <32 x i16> %v7, zeroinitializer
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%v9 = add nuw nsw <32 x i16> %v8, zeroinitializer
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%v10 = add <32 x i16> %v9, zeroinitializer
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%v11 = add <32 x i16> %v10, zeroinitializer
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%v12 = add <32 x i16> %v11, zeroinitializer
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%v13 = add <32 x i16> %v12, zeroinitializer
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%v14 = add <32 x i16> %v13, zeroinitializer
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%v15 = add <32 x i16> %v14, zeroinitializer
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%v16 = add <32 x i16> %v15, zeroinitializer
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%v17 = add <32 x i16> %v16, zeroinitializer
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%v18 = add <32 x i16> %v17, zeroinitializer
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%v19 = lshr <32 x i16> %v18, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
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%v20 = trunc <32 x i16> %v19 to <32 x i8>
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store <32 x i8> %v20, <32 x i8>* @g0, align 1
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ret void
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}
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
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