43e94b15ea
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
34 lines
1.2 KiB
YAML
34 lines
1.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
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--- |
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define void @atomic_memoperands() {
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ret void
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}
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...
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---
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name: atomic_memoperands
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body: |
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bb.0:
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; CHECK-LABEL: name: atomic_memoperands
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load unordered 8)
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; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4)
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; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire 2)
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; CHECK: G_STORE [[LOAD2]](s16), [[COPY]](p0) :: (store release 2)
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; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store acq_rel 4)
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; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store syncscope("singlethread") seq_cst 8)
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; CHECK: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(s64) = G_LOAD %0(p0) :: (load unordered 8)
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%2:_(s32) = G_LOAD %0(p0) :: (load monotonic 4)
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%3:_(s16) = G_LOAD %0(p0) :: (load acquire 2)
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G_STORE %3(s16), %0(p0) :: (store release 2)
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G_STORE %2(s32), %0(p0) :: (store acq_rel 4)
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G_STORE %1(s64), %0(p0) :: (store syncscope("singlethread") seq_cst 8)
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RET_ReallyLR
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...
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