b1c304c494
Memory operands store a base alignment that does not factor in the effect of the offset on the alignment. Previously the printing code only printed the base alignment if it was different than the size. If there is an offset, the reader would need to figure out the effective alignment themselves. This has confused me before and someone else was recently confused on IRC. This patch prints the possibly offset adjusted alignment if it is different than the size. And prints the base alignment if it is different than the alignment. The MIR parser has been updated to read basealign in addition to align. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D94344
149 lines
4.6 KiB
YAML
149 lines
4.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @load_i32(i32* %ptr) {entry: ret void}
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define void @load_i64(i64* %ptr) {entry: ret void}
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define void @load_ambiguous_i64_in_fpr(i64* %i64_ptr_a, i64* %i64_ptr_b) {entry: ret void}
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define void @load_float(float* %ptr) {entry: ret void}
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define void @load_ambiguous_float_in_gpr(float* %float_ptr_a, float* %float_ptr_b) {entry: ret void}
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define void @load_double(double* %ptr) {entry: ret void}
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...
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---
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name: load_i32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load_i32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
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; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.ptr)
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; MIPS32: $v0 = COPY [[LOAD]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(p0) = COPY $a0
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%1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.ptr)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: load_i64
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load_i64
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
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; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.ptr, align 8)
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; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
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; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
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; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[GEP]](p0) :: (load 4 from %ir.ptr + 4, basealign 8)
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; MIPS32: $v0 = COPY [[LOAD]](s32)
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; MIPS32: $v1 = COPY [[LOAD1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(p0) = COPY $a0
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%1:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
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%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
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$v0 = COPY %2(s32)
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$v1 = COPY %3(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: load_ambiguous_i64_in_fpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: load_ambiguous_i64_in_fpr
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
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; MIPS32: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.i64_ptr_a)
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; MIPS32: G_STORE [[LOAD]](s64), [[COPY1]](p0) :: (store 8 into %ir.i64_ptr_b)
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; MIPS32: RetRA
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%0:_(p0) = COPY $a0
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%1:_(p0) = COPY $a1
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%2:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.i64_ptr_a)
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G_STORE %2(s64), %1(p0) :: (store 8 into %ir.i64_ptr_b)
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RetRA
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...
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---
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name: load_float
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load_float
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
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; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.ptr)
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; MIPS32: $f0 = COPY [[LOAD]](s32)
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; MIPS32: RetRA implicit $f0
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%0:_(p0) = COPY $a0
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%1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.ptr)
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$f0 = COPY %1(s32)
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RetRA implicit $f0
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...
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---
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name: load_ambiguous_float_in_gpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: load_ambiguous_float_in_gpr
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
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; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.float_ptr_a)
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; MIPS32: G_STORE [[LOAD]](s32), [[COPY1]](p0) :: (store 4 into %ir.float_ptr_b)
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; MIPS32: RetRA
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%0:_(p0) = COPY $a0
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%1:_(p0) = COPY $a1
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%2:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.float_ptr_a)
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G_STORE %2(s32), %1(p0) :: (store 4 into %ir.float_ptr_b)
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RetRA
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...
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---
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name: load_double
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load_double
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
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; MIPS32: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.ptr)
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; MIPS32: $d0 = COPY [[LOAD]](s64)
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; MIPS32: RetRA implicit $d0
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%0:_(p0) = COPY $a0
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%1:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
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$d0 = COPY %1(s64)
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RetRA implicit $d0
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...
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