00c4e0a8f6
The type legalizer is calling this code based on the scalar type so we need to verify the input type is a scalable vector. The vector type has also not been legalized yet when this is called so we need to use EVT for it.
93 lines
3.5 KiB
LLVM
93 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
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; FIXME: This codegen needs to be improved. These tests previously asserted in
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; ReplaceNodeResults on RV32.
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define i64 @extractelt_v4i64(<4 x i64>* %x) nounwind {
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; RV32-LABEL: extractelt_v4i64:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -64
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; RV32-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
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; RV32-NEXT: addi s0, sp, 64
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; RV32-NEXT: andi sp, sp, -32
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; RV32-NEXT: addi a1, zero, 8
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; RV32-NEXT: vsetvli a1, a1, e32,m2,ta,mu
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; RV32-NEXT: vle32.v v26, (a0)
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; RV32-NEXT: vse32.v v26, (sp)
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; RV32-NEXT: lw a0, 24(sp)
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; RV32-NEXT: lw a1, 28(sp)
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; RV32-NEXT: addi sp, s0, -64
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; RV32-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 64
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; RV32-NEXT: ret
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;
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; RV64-LABEL: extractelt_v4i64:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -64
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; RV64-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
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; RV64-NEXT: addi s0, sp, 64
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; RV64-NEXT: andi sp, sp, -32
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; RV64-NEXT: addi a1, zero, 4
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; RV64-NEXT: vsetvli a1, a1, e64,m2,ta,mu
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; RV64-NEXT: vle64.v v26, (a0)
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; RV64-NEXT: vse64.v v26, (sp)
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; RV64-NEXT: ld a0, 24(sp)
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; RV64-NEXT: addi sp, s0, -64
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; RV64-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 64
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; RV64-NEXT: ret
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%a = load <4 x i64>, <4 x i64>* %x
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%b = extractelement <4 x i64> %a, i32 3
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ret i64 %b
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}
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; This uses a non-power of 2 type so that it isn't an MVT to catch an
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; incorrect use of getSimpleValueType().
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define i64 @extractelt_v3i64(<3 x i64>* %x) nounwind {
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; RV32-LABEL: extractelt_v3i64:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -64
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; RV32-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
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; RV32-NEXT: addi s0, sp, 64
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; RV32-NEXT: andi sp, sp, -32
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; RV32-NEXT: addi a1, zero, 8
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; RV32-NEXT: vsetvli a1, a1, e32,m2,ta,mu
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; RV32-NEXT: vle32.v v26, (a0)
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; RV32-NEXT: vse32.v v26, (sp)
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; RV32-NEXT: lw a0, 16(sp)
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; RV32-NEXT: lw a1, 20(sp)
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; RV32-NEXT: addi sp, s0, -64
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; RV32-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 64
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; RV32-NEXT: ret
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;
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; RV64-LABEL: extractelt_v3i64:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -64
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; RV64-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
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; RV64-NEXT: addi s0, sp, 64
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; RV64-NEXT: andi sp, sp, -32
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; RV64-NEXT: addi a1, zero, 4
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; RV64-NEXT: vsetvli a1, a1, e64,m2,ta,mu
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; RV64-NEXT: vle64.v v26, (a0)
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; RV64-NEXT: vse64.v v26, (sp)
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; RV64-NEXT: ld a0, 16(sp)
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; RV64-NEXT: addi sp, s0, -64
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; RV64-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 64
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; RV64-NEXT: ret
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%a = load <3 x i64>, <3 x i64>* %x
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%b = extractelement <3 x i64> %a, i32 2
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ret i64 %b
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}
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