b2ac9681a7
This changes the definition of t2DoLoopStart from
t2DoLoopStart rGPR
to
GPRlr = t2DoLoopStart rGPR
This will hopefully mean that low overhead loops are more tied together,
and we can more reliably generate loops without reverting or being at
the whims of the register allocator.
This is a fairly simple change in itself, but leads to a number of other
required alterations.
- The hardware loop pass, if UsePhi is set, now generates loops of the
form:
%start = llvm.start.loop.iterations(%N)
loop:
%p = phi [%start], [%dec]
%dec = llvm.loop.decrement.reg(%p, 1)
%c = icmp ne %dec, 0
br %c, loop, exit
- For this a new llvm.start.loop.iterations intrinsic was added, identical
to llvm.set.loop.iterations but produces a value as seen above, gluing
the loop together more through def-use chains.
- This new instrinsic conceptually produces the same output as input,
which is taught to SCEV so that the checks in MVETailPredication are not
affected.
- Some minor changes are needed to the ARMLowOverheadLoop pass, but it has
been left mostly as before. We should now more reliably be able to tell
that the t2DoLoopStart is correct without having to prove it, but
t2WhileLoopStart and tail-predicated loops will remain the same.
- And all the tests have been updated. There are a lot of them!
This patch on it's own might cause more trouble that it helps, with more
tail-predicated loops being reverted, but some additional patches can
hopefully improve upon that to get to something that is better overall.
Differential Revision: https://reviews.llvm.org/D89881
270 lines
12 KiB
YAML
270 lines
12 KiB
YAML
# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
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# CHECK-NOT: t2DLS
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# CHECK: bb.5.for.inc16:
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# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
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# CHECK-NOT: t2CMPri $lr
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# CHECK: tBcc %bb.6, 1 /* CC::ne */
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# CHECK: tB %bb.2
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# CHECK: bb.6.for.cond4.preheader:
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--- |
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; ModuleID = 'revert-non-header.ll'
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source_filename = "revert-non-header.ll"
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main"
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define void @header_not_target_unrolled_loop(i32* nocapture %v, i32 %n) {
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entry:
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%cmp56 = icmp sgt i32 %n, 1
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br i1 %cmp56, label %for.cond1.preheader.preheader, label %for.end20
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for.cond1.preheader.preheader: ; preds = %entry
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br label %for.cond1.preheader
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for.cond.loopexit: ; preds = %for.inc16, %for.cond1.preheader
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%cmp = icmp sgt i32 %gap.057.in, 3
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br i1 %cmp, label %for.cond1.preheader, label %for.end20
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for.cond1.preheader: ; preds = %for.cond1.preheader.preheader, %for.cond.loopexit
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%gap.057.in = phi i32 [ %gap.057, %for.cond.loopexit ], [ %n, %for.cond1.preheader.preheader ]
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%gap.057 = sdiv i32 %gap.057.in, 2
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%cmp252 = icmp slt i32 %gap.057, %n
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%tmp = sub i32 %n, %gap.057
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%start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp)
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br i1 %cmp252, label %for.cond4.preheader.preheader, label %for.cond.loopexit
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for.cond4.preheader.preheader: ; preds = %for.cond1.preheader
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%tmp2 = mul i32 %gap.057, -4
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%tmp6 = mul i32 %gap.057, -2
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%scevgep1 = getelementptr i32, i32* %v, i32 %gap.057
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%0 = shl i32 %gap.057, 2
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br label %for.cond4.preheader
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for.cond4.preheader: ; preds = %for.inc16, %for.cond4.preheader.preheader
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%lsr.iv2 = phi i32* [ %scevgep3, %for.inc16 ], [ %scevgep1, %for.cond4.preheader.preheader ]
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%lsr.iv = phi i32* [ %v, %for.cond4.preheader.preheader ], [ %scevgep, %for.inc16 ]
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%i.053 = phi i32 [ %inc, %for.inc16 ], [ %gap.057, %for.cond4.preheader.preheader ]
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%tmp8 = phi i32 [ %start, %for.cond4.preheader.preheader ], [ %tmp16, %for.inc16 ]
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%j.048 = sub nsw i32 %i.053, %gap.057
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%cmp549 = icmp sgt i32 %j.048, -1
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br i1 %cmp549, label %land.rhs.preheader, label %for.inc16
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land.rhs.preheader: ; preds = %for.cond4.preheader
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br label %land.rhs
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land.rhs: ; preds = %land.rhs.preheader, %for.body8
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%lsr.iv4 = phi i32 [ %lsr.iv.next, %for.body8 ], [ 0, %land.rhs.preheader ]
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%j.051 = phi i32 [ %j.0, %for.body8 ], [ %j.048, %land.rhs.preheader ]
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%1 = bitcast i32* %lsr.iv2 to i8*
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%2 = bitcast i32* %lsr.iv to i8*
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%uglygep3 = getelementptr i8, i8* %2, i32 %lsr.iv4
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%uglygep34 = bitcast i8* %uglygep3 to i32*
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%tmp9 = load i32, i32* %uglygep34, align 4
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%uglygep1 = getelementptr i8, i8* %1, i32 %lsr.iv4
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%uglygep12 = bitcast i8* %uglygep1 to i32*
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%tmp12 = load i32, i32* %uglygep12, align 4
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%cmp7 = icmp sgt i32 %tmp9, %tmp12
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br i1 %cmp7, label %for.body8, label %for.inc16
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for.body8: ; preds = %land.rhs
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%3 = bitcast i32* %lsr.iv2 to i8*
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%4 = bitcast i32* %lsr.iv to i8*
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%sunkaddr = getelementptr i8, i8* %4, i32 %lsr.iv4
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%5 = bitcast i8* %sunkaddr to i32*
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store i32 %tmp12, i32* %5, align 4
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%uglygep = getelementptr i8, i8* %3, i32 %lsr.iv4
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%uglygep6 = bitcast i8* %uglygep to i32*
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store i32 %tmp9, i32* %uglygep6, align 4
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%j.0 = sub nsw i32 %j.051, %gap.057
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%lsr.iv.next = add i32 %lsr.iv4, %0
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%cmp5 = icmp sgt i32 %j.0, -1
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br i1 %cmp5, label %land.rhs, label %for.inc16
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for.inc16: ; preds = %for.body8, %land.rhs, %for.cond4.preheader
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%inc = add nsw i32 %i.053, 1
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%scevgep = getelementptr i32, i32* %lsr.iv, i32 1
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%tmp16 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp8, i32 1)
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%tmp17 = icmp ne i32 %tmp16, 0
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%scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 1
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br i1 %tmp17, label %for.cond4.preheader, label %for.cond.loopexit
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for.end20: ; preds = %for.cond.loopexit, %entry
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ret void
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}
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.start.loop.iterations.i32(i32) #0
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #1
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attributes #0 = { noduplicate nounwind }
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attributes #1 = { nounwind }
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...
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---
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name: header_not_target_unrolled_loop
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 32
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.9(0x40000000)
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liveins: $r0, $r1, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $lr
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$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr
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frame-setup CFI_INSTRUCTION def_cfa_offset 32
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r10, -8
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frame-setup CFI_INSTRUCTION offset $r9, -12
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frame-setup CFI_INSTRUCTION offset $r8, -16
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frame-setup CFI_INSTRUCTION offset $r7, -20
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frame-setup CFI_INSTRUCTION offset $r6, -24
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frame-setup CFI_INSTRUCTION offset $r5, -28
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frame-setup CFI_INSTRUCTION offset $r4, -32
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tCMPi8 renamable $r1, 2, 14, $noreg, implicit-def $cpsr
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tBcc %bb.9, 11, killed $cpsr
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bb.1:
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successors: %bb.3(0x80000000)
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liveins: $r0, $r1
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$r9 = tMOVr $r1, 14, $noreg
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tB %bb.3, 14, $noreg
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bb.2.for.cond.loopexit:
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successors: %bb.3(0x7c000000), %bb.9(0x04000000)
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liveins: $r0, $r1, $r9, $r12
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t2CMPri killed renamable $r12, 4, 14, $noreg, implicit-def $cpsr
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tBcc %bb.9, 11, killed $cpsr
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bb.3.for.cond1.preheader:
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successors: %bb.4(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1, $r9
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renamable $r2 = t2ADDrs $r9, $r9, 251, 14, $noreg, $noreg
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$r12 = tMOVr killed $r9, 14, $noreg
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renamable $lr = t2SUBrs renamable $r1, renamable $r2, 9, 14, $noreg, $noreg
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renamable $r9 = t2ASRri renamable $r2, 1, 14, $noreg, $noreg
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t2CMPrs renamable $r1, killed renamable $r2, 9, 14, $noreg, implicit-def $cpsr
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$lr = t2DoLoopStart renamable $lr
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tBcc %bb.2, 13, killed $cpsr
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bb.4.for.cond4.preheader.preheader:
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successors: %bb.7(0x50000000), %bb.5(0x30000000)
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liveins: $lr, $r0, $r1, $r9, $r12
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renamable $r3 = t2ADDrs renamable $r0, renamable $r9, 18, 14, $noreg, $noreg
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renamable $r10 = t2LSLri renamable $r9, 2, 14, $noreg, $noreg
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$r5 = tMOVr $r0, 14, $noreg
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$r8 = tMOVr $r9, 14, $noreg
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renamable $r7 = nsw t2SUBrr renamable $r8, renamable $r9, 14, $noreg, def $cpsr
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tBcc %bb.7, 5, killed $cpsr
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bb.5.for.inc16:
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successors: %bb.6(0x7c000000), %bb.2(0x04000000)
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liveins: $lr, $r0, $r1, $r3, $r5, $r8, $r9, $r10, $r12
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renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
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renamable $r5, dead $cpsr = tADDi8 killed renamable $r5, 4, 14, $noreg
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renamable $r8 = nsw t2ADDri killed renamable $r8, 1, 14, $noreg, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
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tB %bb.2, 14, $noreg
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bb.6.for.cond4.preheader:
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successors: %bb.7(0x50000000), %bb.5(0x30000000)
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liveins: $lr, $r0, $r1, $r3, $r5, $r8, $r9, $r10, $r12
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renamable $r7 = nsw t2SUBrr renamable $r8, renamable $r9, 14, $noreg, def $cpsr
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tBcc %bb.5, 4, killed $cpsr
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bb.7.land.rhs.preheader:
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successors: %bb.8(0x80000000)
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liveins: $lr, $r0, $r1, $r3, $r5, $r7, $r8, $r9, $r10, $r12
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renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg
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bb.8.land.rhs:
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successors: %bb.5(0x07e00000), %bb.8(0x78200000)
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liveins: $lr, $r0, $r1, $r3, $r5, $r6, $r7, $r8, $r9, $r10, $r12
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renamable $r4 = tLDRr renamable $r3, $r6, 14, $noreg :: (load 4 from %ir.uglygep12)
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renamable $r2 = tLDRr renamable $r5, $r6, 14, $noreg :: (load 4 from %ir.uglygep34)
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tCMPr renamable $r2, renamable $r4, 14, $noreg, implicit-def $cpsr
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t2IT 12, 1, implicit-def $itstate
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tSTRr killed renamable $r4, renamable $r5, $r6, 12, $cpsr, implicit $itstate :: (store 4 into %ir.5)
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tSTRr killed renamable $r2, renamable $r3, $r6, 12, $cpsr, implicit $itstate :: (store 4 into %ir.uglygep6)
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renamable $r6 = tADDhirr killed renamable $r6, renamable $r10, 12, $cpsr, implicit $r6, implicit $itstate
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renamable $r7 = nsw t2SUBrr killed renamable $r7, renamable $r9, 12, $cpsr, $noreg, implicit $r7, implicit killed $itstate
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t2IT 12, 8, implicit-def $itstate
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t2CMPri renamable $r7, -1, 12, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
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tBcc %bb.8, 12, killed $cpsr
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tB %bb.5, 14, $noreg
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bb.9.for.end20:
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$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $pc
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...
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