d9bf6245bf
This adds code to revert low overhead loops with calls in them before register allocation. Ideally we would not create low overhead loops with calls in them to begin with, but that can be difficult to always get correct. If we want to try and glue together t2LoopDec and t2LoopEnd into a single instruction, we need to ensure that no instructions use LR in the loop. (Technically the final code can be better too, as it doesn't need to use the same registers but that has not been optimized for here, as reverting loops with calls is expected to be very rare). It also adds a MVETailPredUtils.h header to share the revert code between different passes, and provides a place to expand upon, with RevertLoopWithCall becoming a place to perform other low overhead loop alterations like removing copies or combining LoopDec and End into a single instruction. Differential Revision: https://reviews.llvm.org/D91273
146 lines
5.1 KiB
YAML
146 lines
5.1 KiB
YAML
# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s --verify-machineinstrs -o - | FileCheck %s
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# CHECK: name: non_loop
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# CHECK: bb.0.entry:
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# CHECK: tBcc %bb.2, 3
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# CHECK: bb.1.not.preheader:
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# CHECK: t2CMPri renamable $lr, 0, 14
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# CHECK: tBcc %bb.4, 0
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# CHECK: tB %bb.2
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# CHECK: bb.3.while.body:
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# CHECK: t2CMPri renamable $lr, 0, 14
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# CHECK: tBcc %bb.3, 1
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# CHECK: tB %bb.4
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# CHECK: bb.4.while.end:
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main"
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define void @non_loop(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) {
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entry:
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%cmp = icmp ugt i32 %N, 2
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br i1 %cmp, label %not.preheader, label %while.body.preheader
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not.preheader: ; preds = %entry
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%test = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
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br i1 %test, label %while.body.preheader, label %while.end
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while.body.preheader: ; preds = %not.preheader, %entry
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%scevgep = getelementptr i16, i16* %a, i32 -1
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%scevgep3 = getelementptr i16, i16* %b, i32 -1
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br label %while.body
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while.body: ; preds = %while.body, %while.body.preheader
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%lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ]
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%lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ]
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%count = phi i32 [ %count.next, %while.body ], [ %N, %while.body.preheader ]
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%scevgep7 = getelementptr i16, i16* %lsr.iv, i32 1
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%scevgep4 = getelementptr i16, i16* %lsr.iv4, i32 1
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%load = load i16, i16* %scevgep4, align 2
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store i16 %load, i16* %scevgep7, align 2
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%count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)
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%cmp1 = icmp ne i32 %count.next, 0
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%scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1
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%scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 1
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br i1 %cmp1, label %while.body, label %while.end
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while.end: ; preds = %while.body, %not.preheader
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ret void
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}
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declare i1 @llvm.test.set.loop.iterations.i32(i32) #0
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
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declare void @llvm.stackprotector(i8*, i8**) #1
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attributes #0 = { noduplicate nounwind }
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attributes #1 = { nounwind }
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...
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---
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name: non_loop
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1, $r2, $r7, $lr
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frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$lr = tMOVr $r2, 14, $noreg
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tCMPi8 killed $r2, 3, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, killed $cpsr
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bb.1.not.preheader:
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successors: %bb.2(0x40000000), %bb.4(0x40000000)
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liveins: $lr, $r0, $r1
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t2WhileLoopStart renamable $lr, %bb.4, implicit-def dead $cpsr
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tB %bb.2, 14, $noreg
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bb.2.while.body.preheader:
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successors: %bb.3(0x80000000)
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liveins: $lr, $r0, $r1
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renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg
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renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg
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bb.3.while.body:
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successors: %bb.3(0x7c000000), %bb.4(0x04000000)
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liveins: $lr, $r0, $r1
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renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4)
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early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7)
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renamable $lr = t2LoopDec killed renamable $lr, 1
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t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
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tB %bb.4, 14, $noreg
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bb.4.while.end:
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tPOP_RET 14, $noreg, def $r7, def $pc
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...
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