322d0afd87
This change renames the intrinsics to not have "experimental" in the name. The autoupgrader will handle legacy intrinsics. Relevant ML thread: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140729.html Differential Revision: https://reviews.llvm.org/D88787
178 lines
5.1 KiB
LLVM
178 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
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declare i64 @llvm.vector.reduce.add.i64.v2i64(<2 x i64>)
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declare i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32>)
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declare i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32>)
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declare i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16>)
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declare i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16>)
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declare i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8>)
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declare i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8>)
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define arm_aapcs_vfpcc i64 @vaddv_v2i64_i64(<2 x i64> %s1) {
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; CHECK-LABEL: vaddv_v2i64_i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: vmov r3, s0
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; CHECK-NEXT: vmov r1, s3
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; CHECK-NEXT: vmov r2, s1
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; CHECK-NEXT: adds r0, r0, r3
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; CHECK-NEXT: adcs r1, r2
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; CHECK-NEXT: bx lr
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entry:
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%r = call i64 @llvm.vector.reduce.add.i64.v2i64(<2 x i64> %s1)
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ret i64 %r
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}
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define arm_aapcs_vfpcc i32 @vaddv_v4i32_i32(<4 x i32> %s1) {
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; CHECK-LABEL: vaddv_v4i32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vaddv.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
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ret i32 %r
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}
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define arm_aapcs_vfpcc i32 @vaddv_v8i32_i32(<8 x i32> %s1) {
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; CHECK-LABEL: vaddv_v8i32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i32 q0, q0, q1
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; CHECK-NEXT: vaddv.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
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ret i32 %r
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}
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define arm_aapcs_vfpcc i16 @vaddv_v8i16_i16(<8 x i16> %s1) {
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; CHECK-LABEL: vaddv_v8i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vaddv.u16 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
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ret i16 %r
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}
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define arm_aapcs_vfpcc i16 @vaddv_v16i16_i16(<16 x i16> %s1) {
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; CHECK-LABEL: vaddv_v16i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i16 q0, q0, q1
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; CHECK-NEXT: vaddv.u16 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
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ret i16 %r
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}
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define arm_aapcs_vfpcc i8 @vaddv_v16i8_i8(<16 x i8> %s1) {
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; CHECK-LABEL: vaddv_v16i8_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vaddv.u8 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
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ret i8 %r
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}
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define arm_aapcs_vfpcc i8 @vaddv_v32i8_i8(<32 x i8> %s1) {
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; CHECK-LABEL: vaddv_v32i8_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i8 q0, q0, q1
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; CHECK-NEXT: vaddv.u8 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
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ret i8 %r
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}
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define arm_aapcs_vfpcc i64 @vaddva_v2i64_i64(<2 x i64> %s1, i64 %x) {
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; CHECK-LABEL: vaddva_v2i64_i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: vmov r2, s2
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; CHECK-NEXT: vmov r3, s0
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; CHECK-NEXT: vmov r12, s3
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; CHECK-NEXT: vmov lr, s1
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; CHECK-NEXT: adds r2, r2, r3
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; CHECK-NEXT: adc.w r3, lr, r12
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; CHECK-NEXT: adds r0, r0, r2
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; CHECK-NEXT: adcs r1, r3
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%t = call i64 @llvm.vector.reduce.add.i64.v2i64(<2 x i64> %s1)
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%r = add i64 %t, %x
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ret i64 %r
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}
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define arm_aapcs_vfpcc i32 @vaddva_v4i32_i32(<4 x i32> %s1, i32 %x) {
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; CHECK-LABEL: vaddva_v4i32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vaddva.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%t = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
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%r = add i32 %t, %x
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ret i32 %r
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}
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define arm_aapcs_vfpcc i32 @vaddva_v8i32_i32(<8 x i32> %s1, i32 %x) {
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; CHECK-LABEL: vaddva_v8i32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i32 q0, q0, q1
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; CHECK-NEXT: vaddva.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%t = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
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%r = add i32 %t, %x
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ret i32 %r
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}
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define arm_aapcs_vfpcc i16 @vaddva_v8i16_i16(<8 x i16> %s1, i16 %x) {
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; CHECK-LABEL: vaddva_v8i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vaddva.u16 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%t = call i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
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%r = add i16 %t, %x
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ret i16 %r
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}
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define arm_aapcs_vfpcc i16 @vaddva_v16i16_i16(<16 x i16> %s1, i16 %x) {
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; CHECK-LABEL: vaddva_v16i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i16 q0, q0, q1
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; CHECK-NEXT: vaddva.u16 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%t = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
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%r = add i16 %t, %x
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ret i16 %r
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}
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define arm_aapcs_vfpcc i8 @vaddva_v16i8_i8(<16 x i8> %s1, i8 %x) {
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; CHECK-LABEL: vaddva_v16i8_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vaddva.u8 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%t = call i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
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%r = add i8 %t, %x
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ret i8 %r
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}
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define arm_aapcs_vfpcc i8 @vaddva_v32i8_i8(<32 x i8> %s1, i8 %x) {
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; CHECK-LABEL: vaddva_v32i8_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.i8 q0, q0, q1
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; CHECK-NEXT: vaddva.u8 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%t = call i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
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%r = add i8 %t, %x
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ret i8 %r
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}
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