Files
clang-p2996/llvm/test/CodeGen/X86/GlobalISel/select-undef.mir
Guillaume Chatelet 48904e9452 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67433

llvm-svn: 371608
2019-09-11 11:16:48 +00:00

89 lines
2.0 KiB
YAML

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
--- |
define i8 @test() {
ret i8 undef
}
define i8 @test2(i8 %a) {
%r = add i8 %a, undef
ret i8 %r
}
define float @test3() {
ret float undef
}
...
---
name: test
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test
; ALL: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
; ALL: $al = COPY [[DEF]]
; ALL: RET 0, implicit $al
%0(s8) = G_IMPLICIT_DEF
$al = COPY %0(s8)
RET 0, implicit $al
...
---
name: test2
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
- { id: 2, class: gpr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
liveins: $edi
; ALL-LABEL: name: test2
; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil
; ALL: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
; ALL: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[DEF]], implicit-def $eflags
; ALL: $al = COPY [[ADD8rr]]
; ALL: RET 0, implicit $al
%0(s8) = COPY $dil
%1(s8) = G_IMPLICIT_DEF
%2(s8) = G_ADD %0, %1
$al = COPY %2(s8)
RET 0, implicit $al
...
---
name: test3
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 1, class: vecr }
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test3
; ALL: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF
; ALL: $xmm0 = COPY [[DEF]]
; ALL: RET 0, implicit $xmm0
%1:vecr(s128) = G_IMPLICIT_DEF
$xmm0 = COPY %1:vecr(s128)
RET 0, implicit $xmm0
...