80aa2290fb
Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
233 lines
6.7 KiB
YAML
233 lines
6.7 KiB
YAML
# RUN: llc -mtriple=x86_64-- -run-pass=peephole-opt -o - %s | FileCheck %s
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--- |
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define i32 @foo(i32 %a) {
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bb0:
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br label %bb1
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bb1: ; preds = %bb7, %bb0
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%vreg0 = phi i32 [ 0, %bb0 ], [ %vreg3, %bb7 ]
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%cond0 = icmp eq i32 %a, 0
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br i1 %cond0, label %bb4, label %bb3
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bb3: ; preds = %bb1
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br label %bb4
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bb4: ; preds = %bb1, %bb3
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%vreg5 = phi i32 [ 2, %bb3 ], [ 1, %bb1 ]
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%cond1 = icmp eq i32 %vreg5, 0
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br i1 %cond1, label %bb7, label %bb6
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bb6: ; preds = %bb4
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br label %bb7
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bb7: ; preds = %bb4, %bb6
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%vreg1 = phi i32 [ 2, %bb6 ], [ 1, %bb4 ]
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%vreg2 = add i32 %vreg5, %vreg0
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%vreg3 = add i32 %vreg1, %vreg2
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%cond2 = icmp slt i32 %vreg3, 10
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br i1 %cond2, label %bb1, label %bb8
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bb8: ; preds = %bb7
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ret i32 0
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}
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define i32 @bar(i32 %a, i32* %p) {
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bb0:
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br label %bb1
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bb1: ; preds = %bb7, %bb0
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%vreg0 = phi i32 [ 0, %bb0 ], [ %vreg3, %bb7 ]
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%cond0 = icmp eq i32 %a, 0
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br i1 %cond0, label %bb4, label %bb3
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bb3: ; preds = %bb1
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br label %bb4
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bb4: ; preds = %bb1, %bb3
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%vreg5 = phi i32 [ 2, %bb3 ], [ 1, %bb1 ]
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%cond1 = icmp eq i32 %vreg5, 0
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br i1 %cond1, label %bb7, label %bb6
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bb6: ; preds = %bb4
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br label %bb7
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bb7: ; preds = %bb4, %bb6
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%vreg1 = phi i32 [ 2, %bb6 ], [ 1, %bb4 ]
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%vreg2 = add i32 %vreg5, %vreg0
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store i32 %vreg0, i32* %p
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%vreg3 = add i32 %vreg1, %vreg2
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%cond2 = icmp slt i32 %vreg3, 10
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br i1 %cond2, label %bb1, label %bb8
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bb8: ; preds = %bb7
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ret i32 0
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}
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...
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---
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# There is a recurrence formulated around %0, %10, and %3. Check that operands
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# are commuted for ADD instructions in bb.5.bb7 so that the values involved in
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# the recurrence are tied. This will remove redundant copy instruction.
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name: foo
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32, preferred-register: '' }
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- { id: 1, class: gr32, preferred-register: '' }
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- { id: 2, class: gr32, preferred-register: '' }
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- { id: 3, class: gr32, preferred-register: '' }
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- { id: 4, class: gr32, preferred-register: '' }
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- { id: 5, class: gr32, preferred-register: '' }
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- { id: 6, class: gr32, preferred-register: '' }
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- { id: 7, class: gr32, preferred-register: '' }
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- { id: 8, class: gr32, preferred-register: '' }
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- { id: 9, class: gr32, preferred-register: '' }
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- { id: 10, class: gr32, preferred-register: '' }
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- { id: 11, class: gr32, preferred-register: '' }
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- { id: 12, class: gr32, preferred-register: '' }
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liveins:
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- { reg: '$edi', virtual-reg: '%4' }
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body: |
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bb.0.bb0:
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successors: %bb.1(0x80000000)
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liveins: $edi
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%4 = COPY $edi
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%5 = MOV32r0 implicit-def dead $eflags
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bb.1.bb1:
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successors: %bb.3(0x30000000), %bb.2(0x50000000)
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; CHECK: %0:gr32 = PHI %5, %bb.0, %3, %bb.5
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%0 = PHI %5, %bb.0, %3, %bb.5
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%6 = MOV32ri 1
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TEST32rr %4, %4, implicit-def $eflags
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JCC_1 %bb.3, 4, implicit $eflags
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JMP_1 %bb.2
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bb.2.bb3:
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successors: %bb.3(0x80000000)
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%7 = MOV32ri 2
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bb.3.bb4:
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successors: %bb.5(0x30000000), %bb.4(0x50000000)
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%1 = PHI %6, %bb.1, %7, %bb.2
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TEST32rr %1, %1, implicit-def $eflags
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JCC_1 %bb.5, 4, implicit $eflags
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JMP_1 %bb.4
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bb.4.bb6:
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successors: %bb.5(0x80000000)
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%9 = MOV32ri 2
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bb.5.bb7:
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successors: %bb.1(0x7c000000), %bb.6(0x04000000)
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%2 = PHI %6, %bb.3, %9, %bb.4
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%10 = ADD32rr %1, %0, implicit-def dead $eflags
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; CHECK: %10:gr32 = ADD32rr
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; CHECK-SAME: %0,
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; CHECK-SAME: %1,
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%3 = ADD32rr %2, killed %10, implicit-def dead $eflags
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; CHECK: %3:gr32 = ADD32rr
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; CHECK-SAME: %10,
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; CHECK-SAME: %2,
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%11 = SUB32ri8 %3, 10, implicit-def $eflags
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JCC_1 %bb.1, 12, implicit $eflags
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JMP_1 %bb.6
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bb.6.bb8:
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%12 = MOV32r0 implicit-def dead $eflags
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$eax = COPY %12
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RET 0, $eax
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...
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---
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# Here a recurrence is formulated around %0, %11, and %3, but operands should
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# not be commuted because %0 has a use outside of recurrence. This is to
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# prevent the case of commuting operands ties the values with overlapping live
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# ranges.
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name: bar
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32, preferred-register: '' }
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- { id: 1, class: gr32, preferred-register: '' }
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- { id: 2, class: gr32, preferred-register: '' }
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- { id: 3, class: gr32, preferred-register: '' }
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- { id: 4, class: gr32, preferred-register: '' }
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- { id: 5, class: gr64, preferred-register: '' }
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- { id: 6, class: gr32, preferred-register: '' }
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- { id: 7, class: gr32, preferred-register: '' }
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- { id: 8, class: gr32, preferred-register: '' }
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- { id: 9, class: gr32, preferred-register: '' }
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- { id: 10, class: gr32, preferred-register: '' }
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- { id: 11, class: gr32, preferred-register: '' }
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- { id: 12, class: gr32, preferred-register: '' }
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- { id: 13, class: gr32, preferred-register: '' }
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liveins:
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- { reg: '$edi', virtual-reg: '%4' }
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- { reg: '$rsi', virtual-reg: '%5' }
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body: |
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bb.0.bb0:
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successors: %bb.1(0x80000000)
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liveins: $edi, $rsi
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%5 = COPY $rsi
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%4 = COPY $edi
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%6 = MOV32r0 implicit-def dead $eflags
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bb.1.bb1:
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successors: %bb.3(0x30000000), %bb.2(0x50000000)
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%0 = PHI %6, %bb.0, %3, %bb.5
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; CHECK: %0:gr32 = PHI %6, %bb.0, %3, %bb.5
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%7 = MOV32ri 1
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TEST32rr %4, %4, implicit-def $eflags
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JCC_1 %bb.3, 4, implicit $eflags
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JMP_1 %bb.2
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bb.2.bb3:
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successors: %bb.3(0x80000000)
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%8 = MOV32ri 2
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bb.3.bb4:
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successors: %bb.5(0x30000000), %bb.4(0x50000000)
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%1 = PHI %7, %bb.1, %8, %bb.2
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TEST32rr %1, %1, implicit-def $eflags
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JCC_1 %bb.5, 4, implicit $eflags
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JMP_1 %bb.4
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bb.4.bb6:
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successors: %bb.5(0x80000000)
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%10 = MOV32ri 2
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bb.5.bb7:
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successors: %bb.1(0x7c000000), %bb.6(0x04000000)
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%2 = PHI %7, %bb.3, %10, %bb.4
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%11 = ADD32rr %1, %0, implicit-def dead $eflags
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; CHECK: %11:gr32 = ADD32rr
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; CHECK-SAME: %1,
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; CHECK-SAME: %0,
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MOV32mr %5, 1, $noreg, 0, $noreg, %0 :: (store 4 into %ir.p)
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%3 = ADD32rr %2, killed %11, implicit-def dead $eflags
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; CHECK: %3:gr32 = ADD32rr
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; CHECK-SAME: %2,
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; CHECK-SAME: %11,
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%12 = SUB32ri8 %3, 10, implicit-def $eflags
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JCC_1 %bb.1, 12, implicit $eflags
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JMP_1 %bb.6
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bb.6.bb8:
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%13 = MOV32r0 implicit-def dead $eflags
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$eax = COPY %13
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RET 0, $eax
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...
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