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clang-p2996/llvm/test/MC/X86
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Craig Topper c691fe14da [X86] Accept 64-bit GPRs for vextractps when using a register that requires EVEX. 
This is consistent with the VEX version. It also fixes a sorting
issue in the matching table that caused the EVEX version to be
prioritized over VEX in intel syntax.

Fixes issue [2] from PR48991.
2021-02-01 11:01:32 -08:00
..
AlignedBundling
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
AMX
[X86-64] Support Intel AMX instructions
2020-07-02 08:57:04 +08:00
Inputs
[NFC][X86] Simplify test cases for branch align
2020-03-16 16:30:29 +08:00
KEYLOCKER
[X86] Support Intel Key Locker
2020-09-30 18:08:45 +08:00
3DNow.s
…
2011-09-06-NoNewline.s
…
abs8.s
…
addr16-32.s
[X86] Add segment and address-size override prefixes
2021-01-19 23:54:31 -08:00
address-size.s
…
AES-32.s
…
AES-64.s
…
align-branch-32bit.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-align.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-basic.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-boundary-default.s
[NFC][X86] Simplify test cases for branch align
2020-03-16 16:30:29 +08:00
align-branch-bundle.s
[X86] Enable multibyte NOPs in 64-bit mode for padding/alignment.
2020-07-01 23:59:01 -07:00
align-branch-enhanced-relaxation.s
[X86][MC] Support enhanced relaxation for branch align
2020-04-08 19:08:19 +08:00
align-branch-fused.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-general.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-hardcode.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-mixed.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-necessary.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-negative.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-pad-max-prefix.s
[X86] Enable multibyte NOPs in 64-bit mode for padding/alignment.
2020-07-01 23:59:01 -07:00
align-branch-prefix.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-relax-all.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-section-size.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
align-branch-section-type.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
align-branch-single.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-system.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-branch-variant-symbol.s
[NFC][test] Refine tests for branch align
2020-04-11 13:04:52 +08:00
align-via-padding-corner.s
[X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g
2021-01-16 16:39:54 -08:00
align-via-padding.s
[X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g
2021-01-16 16:39:54 -08:00
align-via-relaxation.s
[X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g
2021-01-16 16:39:54 -08:00
avx512_bf16_vl-encoding.s
…
avx512_bf16-encoding.s
…
avx512-encodings.s
…
avx512-err.s
[X86][llvm-mc] Make the suffix matcher more accurate.
2020-05-27 14:45:17 +08:00
avx512bitalg-encoding.s
…
avx512bw-encoding.s
…
avx512gfni-encoding.s
…
avx512ifma-encoding.s
…
avx512ifmavl-encoding.s
…
avx512vaes-encoding.s
…
avx512vbmi2-encoding.s
…
avx512vbmi2vl-encoding.s
…
avx512vbmi-encoding.s
…
avx512vl_bitalg-encoding.s
…
avx512vl_gfni-encoding.s
…
avx512vl_vaes-encoding.s
…
avx512vl_vnni-encoding.s
…
avx512vl-encoding.s
…
avx512vlvpclmul.s
…
avx512vnni-encoding.s
…
avx512vp2intersectvl-att.s
…
avx512vp2intersectvl-intel.s
…
avx512vpclmul.s
…
avx5124fmaps-encoding.s
…
avx5124vnniw-encoding.s
…
AVX2-32.s
…
AVX2-64.s
…
AVX512F_512-32.s
…
AVX512F_512-64.s
…
AVX512F_SCALAR-32.s
…
AVX512F_SCALAR-64.s
…
avx_vaes-encoding.s
…
avx_vnni-encoding.s
[X86] Support Intel avxvnni
2020-10-31 12:39:51 +08:00
AVX-32.s
…
AVX-64.s
…
AVXAES-32.s
…
AVXAES-64.s
…
BMI1-32.s
…
BMI1-64.s
…
BMI2-32.s
…
BMI2-64.s
…
CET-32.s
…
CET-64.s
…
cet-encoding.s
…
cfi_offset-eip.s
[MC][test] Reorganize .cfi_* tests
2020-12-21 17:18:28 -08:00
check-end-of-data-region.s
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
CLFLUSHOPT-32.s
…
CLFLUSHOPT-64.s
…
CLFSH-32.s
…
CLFSH-64.s
…
CLWB-32.s
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CLWB-64.s
…
CLZERO-32.s
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CLZERO-64.s
…
code16-32-64.s
[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
2020-03-05 18:05:28 -08:00
code16gcc.s
[X86] Properly encode a 32-bit address with an index register and no base register in 16-bit mode.
2020-07-27 21:11:42 -07:00
compact-unwind-cfi_def_cfa.s
[MC][test] Reorganize .cfi_* tests
2020-12-21 17:18:28 -08:00
compact-unwind.s
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
crlf.test
…
data-prefix16.s
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
data-prefix32.s
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
data-prefix64.s
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
data-prefix-fail.s
[X86] .code16: temporarily set Mode32Bit when matching an instruction with the data32 prefix
2020-10-06 08:32:03 -07:00
directive-arch.s
[X86] Parse and ignore .arch directives
2020-07-30 08:30:06 -07:00
disassemble-zeroes.s
[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
2020-03-05 18:05:28 -08:00
dwarf-size-field-overflow.test
…
encoder-fail.s
[X86] Remove period from end of error message in assembler
2020-10-21 00:43:23 -07:00
error-reloc.s
…
eval-fill.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
F16C-32.s
…
F16C-64.s
…
faultmap-section-parsing.s
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
fixup-cpu-mode.s
…
FMA-32.s
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FMA-64.s
…
fp-setup-macho.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
FXSAVE64-64.s
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FXSAVE-32.s
…
FXSAVE-64.s
…
gather.s
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gfni-encoding.s
…
gnux32-dwarf-gen.s
…
gotpcrelx.s
[X86] Avoid generating invalid R_X86_64_GOTPCRELX relocations
2020-12-18 23:38:38 +00:00
hex-immediates.s
…
i386-darwin-frame-register.ll
Show register names in DWARF unwind info.
2020-10-05 15:34:33 -07:00
I86-32.s
…
I86-64.s
…
I186-32.s
…
I186-64.s
…
I286-32.s
[X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register.
2020-07-15 23:51:37 -07:00
I286-64.s
[X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register.
2020-07-15 23:51:37 -07:00
I386-32.s
…
I386-64.s
…
I486-32.s
…
I486-64.s
…
imm-comments.s
…
index-operations.s
…
inline-asm-obj.ll
…
intel-syntax-2.s
…
intel-syntax-32.s
…
intel-syntax-ambiguous.s
…
intel-syntax-avx512_bf16_vl.s
…
intel-syntax-avx512_bf16.s
…
intel-syntax-avx512-error.s
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intel-syntax-avx512.s
…
intel-syntax-avx_vnni.s
[X86] Support Intel avxvnni
2020-10-31 12:39:51 +08:00
intel-syntax-bitwise-ops.s
…
intel-syntax-directional-label.s
…
intel-syntax-encoding.s
…
intel-syntax-error.s
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intel-syntax-hex.s
…
intel-syntax-invalid-basereg.s
…
intel-syntax-invalid-scale.s
…
intel-syntax-print.ll
…
intel-syntax-ptr-sized.s
…
intel-syntax-unsized-memory.s
…
intel-syntax-var-offset.ll
[test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:47:16 -08:00
intel-syntax-x86-64-avx512_bf16_vl.s
…
intel-syntax-x86-64-avx512_bf16.s
…
intel-syntax-x86-64-avx512f_vl.s
[X86] Accept 64-bit GPRs for vextractps when using a register that requires EVEX.
2021-02-01 11:01:32 -08:00
intel-syntax-x86-64-avx_vnni.s
[X86] Support Intel avxvnni
2020-10-31 12:39:51 +08:00
intel-syntax-x86-64-avx.s
[X86] Accept 64-bit GPRs for vextractps when using a register that requires EVEX.
2021-02-01 11:01:32 -08:00
intel-syntax-x86-avx512dq_vl.s
…
intel-syntax-x86-avx512vbmi_vl.s
…
intel-syntax.s
…
invalid_opcode.s
…
invalid-sleb.s
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
INVPCID-32.s
…
INVPCID-64.s
…
large-bss.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
line-table-sections.s
…
lit.local.cfg
…
LWP-32.s
…
LWP-64.s
…
lwp-x86_64.s
…
lwp.s
…
macho-reloc-errors-x86_64.s
…
macho-reloc-errors-x86.s
…
macho-uleb.s
…
MMX-32.s
…
MMX-64.s
…
mpx-encodings.s
…
no-elf-compact-unwind.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
padlock.s
[X86] Force VIA PadLock crypto instructions to emit a 0xF3 prefix when they encode to match what GNU as does.
2020-06-11 12:59:21 -07:00
PKU-32.s
…
PKU-64.s
…
pltoff.s
[X86] Support modifier @PLTOFF for R_X86_64_PLTOFF64
2020-12-01 08:39:01 -08:00
POPCNT-32.s
…
POPCNT-64.s
…
PPRO-32.s
…
PPRO-64.s
…
pr22004.s
…
pr22028.s
…
pr27884.s
…
pr28547.s
…
pr32530.s
…
pr37425.s
…
PREFETCH-32.s
…
PREFETCH-64.s
…
prefix-padding-32.s
[X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g
2021-01-16 16:39:54 -08:00
prefix-padding-64.s
[X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g
2021-01-16 16:39:54 -08:00
RDPMC-32.s
…
RDPMC-64.s
…
RDRAND-32.s
…
RDRAND-64.s
…
RDSEED-32.s
…
RDSEED-64.s
…
RDTSCP-32.s
…
RDTSCP-64.s
…
RDWRFSGS-64.s
…
relax-insn.s
…
relax-offset.s
[MC] Recalculate fragment offsets after relaxation
2020-03-17 14:48:05 -07:00
reloc-directive-elf-32.s
[llvm-readobj] - For SHT_REL relocations, don't display an addend.
2020-12-14 12:03:00 +03:00
reloc-directive-elf-64.s
[MC][X86] Make .reloc support arbitrary relocation types
2020-03-27 13:33:15 -07:00
reloc-directive.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
reloc-macho.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
reloc-undef-global.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
ret.s
…
RTM.s
…
segment-prefix.s
[X86] Add segment and address-size override prefixes
2021-01-19 23:54:31 -08:00
SHA-32.s
…
SHA-64.s
…
shuffle-comments.s
…
signed-coff-pcrel.s
…
SNP-32.s
[X86] Add TLBSYNC, INVLPGB and SNP instructions
2021-01-08 22:28:53 +05:30
SNP-64.s
[X86] Add TLBSYNC, INVLPGB and SNP instructions
2021-01-08 22:28:53 +05:30
space-err.s
…
SSE2-32.s
…
SSE2-64.s
…
SSE3-32.s
…
SSE3-64.s
…
SSE4a-32.s
…
SSE4a-64.s
…
SSE41-32.s
…
SSE41-64.s
…
SSE42-32.s
…
SSE42-64.s
…
SSE_PREFETCH-32.s
…
SSE_PREFETCH-64.s
…
SSE-32.s
…
SSE-64.s
…
SSEMXCSR-32.s
…
SSEMXCSR-64.s
…
SSSE3-32.s
…
SSSE3-64.s
…
stackmap-nops.ll
…
stdcall.s
…
SVM-32.s
[X86] Teach assembler to accept vmsave/vmload/vmrun/invlpga/skinit with or without the fixed register operands
2020-12-19 11:01:55 -08:00
SVM-64.s
[X86] Teach assembler to accept vmsave/vmload/vmrun/invlpga/skinit with or without the fixed register operands
2020-12-19 11:01:55 -08:00
tlsdesc-32.s
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
tlsdesc-64.s
[llvm-objdump] Print target address with evaluateMemoryOperandAddress()
2020-04-27 09:43:51 -07:00
tlsdesc-x32.s
[X86] Add REX prefix for GOTTPOFF/TLSDESC relocs in x32 mode
2020-12-15 23:07:34 +00:00
unused_reg_var_assign.s
…
validate-inst-att.s
…
validate-inst-intel.s
…
variant-diagnostics.s
…
VMFUNC-32.s
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VMFUNC-64.s
…
vpclmulqdq.s
…
VTX-32.s
…
VTX-64.s
…
x86_64-asm-match.s
…
x86_64-avx-clmul-encoding.s
…
x86_64-avx-encoding.s
…
x86_64-bmi-encoding.s
…
x86_64-directive-nops.s
[X86] support .nops directive
2020-08-03 11:50:56 -07:00
x86_64-encoding.s
…
x86_64-fma3-encoding.s
…
x86_64-fma4-encoding.s
…
x86_64-hle-encoding.s
…
x86_64-imm-widths.s
…
x86_64-rand-encoding.s
…
x86_64-rtm-encoding.s
…
x86_64-signed-reloc.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
x86_64-sse4a.s
…
x86_64-tbm-encoding.s
…
x86_64-xop-encoding.s
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x86_directives.s
…
x86_errors.s
[X86] Add assembler support for {vex} prefix to match GNU as.
2020-05-08 11:50:58 -07:00
x86_long_nop.s
[X86] Update tests for znver3
2021-01-07 11:51:50 +05:30
x86_nop.s
…
x86_operands.s
…
x86-16.s
[X86] .code16: temporarily set Mode32Bit when matching an instruction with the data32 prefix
2020-10-06 08:32:03 -07:00
x86-32-avx512_vp2intersect-intel.s
…
x86-32-avx512vp2intersect-att.s
…
x86-32-avx.s
…
x86-32-coverage.s
[X86] Add TLBSYNC, INVLPGB and SNP instructions
2021-01-08 22:28:53 +05:30
x86-32-fma3.s
…
x86-32-ms-inline-asm.s
…
x86-32.s
[X86] Add TLBSYNC, INVLPGB and SNP instructions
2021-01-08 22:28:53 +05:30
x86-64-avx512_bf16_vl-encoding.s
…
x86-64-avx512_bf16-encoding.s
…
x86-64-avx512_vp2intersect-intel.s
…
x86-64-avx512bw_vl.s
…
x86-64-avx512bw.s
…
x86-64-avx512cd_vl.s
…
x86-64-avx512cd.s
…
x86-64-avx512dq_vl.s
…
x86-64-avx512dq.s
…
x86-64-avx512f_vl.s
…
x86-64-avx512pf.s
…
x86-64-avx512vp2intersect-att.s
…
x86-64-avx512vp2intersectvl-att.s
…
x86-64-avx512vp2intersectvl-intel.s
…
x86-64-avx512vpopcntdq.s
…
x86-64-avx_vnni-encoding.s
[X86] Support Intel avxvnni
2020-10-31 12:39:51 +08:00
x86-64.s
[X86] Add TLBSYNC, INVLPGB and SNP instructions
2021-01-08 22:28:53 +05:30
x86-branch-relaxation.s
[X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form
2020-03-26 08:28:59 -07:00
x86-directive-nops-errors.s
[X86] support .nops directive
2020-08-03 11:50:56 -07:00
x86-directive-nops.s
[X86] support .nops directive
2020-08-03 11:50:56 -07:00
x86-evenDirective.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
x86-GCC-inline-asm-Y-constraints.ll
[X86] Remove support for Y0 constraint as an alias for Yz in inline assembly.
2020-05-06 14:58:53 -07:00
x86-itanium.ll
…
x86-jcxz-loop-fixup.s
…
x86-target-directives.s
…
x86-windows-itanium-libcalls.ll
…
X86_64-pku.s
…
X87-32.s
…
X87-64.s
…
XOP-32.s
…
XOP-64.s
…
XSAVE-32.s
…
XSAVE-64.s
…
XSAVEC-32.s
…
XSAVEC-64.s
…
XSAVEOPT-32.s
…
XSAVEOPT-64.s
…
XSAVES-32.s
…
XSAVES-64.s
…