e9628955f5
Recently, restrictions on vector reductions were made more relaxed by accepting any width signless integer and floating-point. This CL relaxes the restriction even more by including unsigned and signed integers. Reviewed By: bkramer Differential Revision: https://reviews.llvm.org/D88442
44 lines
1.2 KiB
MLIR
44 lines
1.2 KiB
MLIR
// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm -convert-std-to-llvm | \
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// RUN: mlir-cpu-runner -e entry -entry-point-result=void \
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// RUN: -shared-libs=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
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// RUN: FileCheck %s
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func @entry() {
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%v = std.constant dense<[-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7]> : vector<16xsi4>
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vector.print %v : vector<16xsi4>
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//
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// Test vector:
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//
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// CHECK: ( -8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7 )
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%0 = vector.reduction "add", %v : vector<16xsi4> into si4
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vector.print %0 : si4
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// CHECK: -8
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%1 = vector.reduction "mul", %v : vector<16xsi4> into si4
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vector.print %1 : si4
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// CHECK: 0
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%2 = vector.reduction "min", %v : vector<16xsi4> into si4
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vector.print %2 : si4
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// CHECK: -8
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%3 = vector.reduction "max", %v : vector<16xsi4> into si4
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vector.print %3 : si4
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// CHECK: 7
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%4 = vector.reduction "and", %v : vector<16xsi4> into si4
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vector.print %4 : si4
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// CHECK: 0
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%5 = vector.reduction "or", %v : vector<16xsi4> into si4
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vector.print %5 : si4
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// CHECK: -1
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%6 = vector.reduction "xor", %v : vector<16xsi4> into si4
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vector.print %6 : si4
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// CHECK: 0
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return
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}
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