bd30a796fc
Continue the convergence between LLVM dialect and built-in types by using the built-in vector type whenever possible, that is for fixed vectors of built-in integers and built-in floats. LLVM dialect vector type is still in use for pointers, less frequent floating point types that do not have a built-in equivalent, and scalable vectors. However, the top-level `LLVMVectorType` class has been removed in favor of free functions capable of inspecting both built-in and LLVM dialect vector types: `LLVM::getVectorElementType`, `LLVM::getNumVectorElements` and `LLVM::getFixedVectorType`. Additional work is necessary to design an implemented the extensions to built-in types so as to remove the `LLVMFixedVectorType` entirely. Note that the default output format for the built-in vectors does not have whitespace around the `x` separator, e.g., `vector<4xf32>` as opposed to the LLVM dialect vector type format that does, e.g., `!llvm.vec<4 x fp128>`. This required changing the FileCheck patterns in several tests. Reviewed By: mehdi_amini, silvas Differential Revision: https://reviews.llvm.org/D94405
122 lines
5.2 KiB
MLIR
122 lines
5.2 KiB
MLIR
// RUN: mlir-opt -convert-spirv-to-llvm %s | FileCheck %s
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//===----------------------------------------------------------------------===//
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// spv.ShiftRightArithmetic
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @shift_right_arithmetic_scalar
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spv.func @shift_right_arithmetic_scalar(%arg0: i32, %arg1: si32, %arg2 : i16, %arg3 : ui16) "None" {
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// CHECK: llvm.ashr %{{.*}}, %{{.*}} : i32
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%0 = spv.ShiftRightArithmetic %arg0, %arg0 : i32, i32
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// CHECK: llvm.ashr %{{.*}}, %{{.*}} : i32
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%1 = spv.ShiftRightArithmetic %arg0, %arg1 : i32, si32
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// CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i32
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// CHECK: llvm.ashr %{{.*}}, %[[SEXT]] : i32
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%2 = spv.ShiftRightArithmetic %arg0, %arg2 : i32, i16
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// CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : i16 to i32
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// CHECK: llvm.ashr %{{.*}}, %[[ZEXT]] : i32
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%3 = spv.ShiftRightArithmetic %arg0, %arg3 : i32, ui16
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spv.Return
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}
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// CHECK-LABEL: @shift_right_arithmetic_vector
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spv.func @shift_right_arithmetic_vector(%arg0: vector<4xi64>, %arg1: vector<4xui64>, %arg2: vector<4xi32>, %arg3: vector<4xui32>) "None" {
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// CHECK: llvm.ashr %{{.*}}, %{{.*}} : vector<4xi64>
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%0 = spv.ShiftRightArithmetic %arg0, %arg0 : vector<4xi64>, vector<4xi64>
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// CHECK: llvm.ashr %{{.*}}, %{{.*}} : vector<4xi64>
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%1 = spv.ShiftRightArithmetic %arg0, %arg1 : vector<4xi64>, vector<4xui64>
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// CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64>
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// CHECK: llvm.ashr %{{.*}}, %[[SEXT]] : vector<4xi64>
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%2 = spv.ShiftRightArithmetic %arg0, %arg2 : vector<4xi64>, vector<4xi32>
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// CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : vector<4xi32> to vector<4xi64>
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// CHECK: llvm.ashr %{{.*}}, %[[ZEXT]] : vector<4xi64>
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%3 = spv.ShiftRightArithmetic %arg0, %arg3 : vector<4xi64>, vector<4xui32>
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spv.Return
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}
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//===----------------------------------------------------------------------===//
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// spv.ShiftRightLogical
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @shift_right_logical_scalar
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spv.func @shift_right_logical_scalar(%arg0: i32, %arg1: si32, %arg2 : si16, %arg3 : ui16) "None" {
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// CHECK: llvm.lshr %{{.*}}, %{{.*}} : i32
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%0 = spv.ShiftRightLogical %arg0, %arg0 : i32, i32
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// CHECK: llvm.lshr %{{.*}}, %{{.*}} : i32
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%1 = spv.ShiftRightLogical %arg0, %arg1 : i32, si32
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// CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i32
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// CHECK: llvm.lshr %{{.*}}, %[[SEXT]] : i32
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%2 = spv.ShiftRightLogical %arg0, %arg2 : i32, si16
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// CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : i16 to i32
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// CHECK: llvm.lshr %{{.*}}, %[[ZEXT]] : i32
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%3 = spv.ShiftRightLogical %arg0, %arg3 : i32, ui16
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spv.Return
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}
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// CHECK-LABEL: @shift_right_logical_vector
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spv.func @shift_right_logical_vector(%arg0: vector<4xi64>, %arg1: vector<4xsi64>, %arg2: vector<4xi32>, %arg3: vector<4xui32>) "None" {
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// CHECK: llvm.lshr %{{.*}}, %{{.*}} : vector<4xi64>
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%0 = spv.ShiftRightLogical %arg0, %arg0 : vector<4xi64>, vector<4xi64>
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// CHECK: llvm.lshr %{{.*}}, %{{.*}} : vector<4xi64>
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%1 = spv.ShiftRightLogical %arg0, %arg1 : vector<4xi64>, vector<4xsi64>
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// CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64>
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// CHECK: llvm.lshr %{{.*}}, %[[SEXT]] : vector<4xi64>
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%2 = spv.ShiftRightLogical %arg0, %arg2 : vector<4xi64>, vector<4xi32>
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// CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : vector<4xi32> to vector<4xi64>
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// CHECK: llvm.lshr %{{.*}}, %[[ZEXT]] : vector<4xi64>
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%3 = spv.ShiftRightLogical %arg0, %arg3 : vector<4xi64>, vector<4xui32>
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spv.Return
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}
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//===----------------------------------------------------------------------===//
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// spv.ShiftLeftLogical
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @shift_left_logical_scalar
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spv.func @shift_left_logical_scalar(%arg0: i32, %arg1: si32, %arg2 : i16, %arg3 : ui16) "None" {
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// CHECK: llvm.shl %{{.*}}, %{{.*}} : i32
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%0 = spv.ShiftLeftLogical %arg0, %arg0 : i32, i32
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// CHECK: llvm.shl %{{.*}}, %{{.*}} : i32
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%1 = spv.ShiftLeftLogical %arg0, %arg1 : i32, si32
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// CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i32
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// CHECK: llvm.shl %{{.*}}, %[[SEXT]] : i32
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%2 = spv.ShiftLeftLogical %arg0, %arg2 : i32, i16
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// CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : i16 to i32
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// CHECK: llvm.shl %{{.*}}, %[[ZEXT]] : i32
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%3 = spv.ShiftLeftLogical %arg0, %arg3 : i32, ui16
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spv.Return
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}
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// CHECK-LABEL: @shift_left_logical_vector
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spv.func @shift_left_logical_vector(%arg0: vector<4xi64>, %arg1: vector<4xsi64>, %arg2: vector<4xi32>, %arg3: vector<4xui32>) "None" {
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// CHECK: llvm.shl %{{.*}}, %{{.*}} : vector<4xi64>
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%0 = spv.ShiftLeftLogical %arg0, %arg0 : vector<4xi64>, vector<4xi64>
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// CHECK: llvm.shl %{{.*}}, %{{.*}} : vector<4xi64>
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%1 = spv.ShiftLeftLogical %arg0, %arg1 : vector<4xi64>, vector<4xsi64>
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// CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64>
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// CHECK: llvm.shl %{{.*}}, %[[SEXT]] : vector<4xi64>
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%2 = spv.ShiftLeftLogical %arg0, %arg2 : vector<4xi64>, vector<4xi32>
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// CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : vector<4xi32> to vector<4xi64>
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// CHECK: llvm.shl %{{.*}}, %[[ZEXT]] : vector<4xi64>
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%3 = spv.ShiftLeftLogical %arg0, %arg3 : vector<4xi64>, vector<4xui32>
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spv.Return
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}
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