903eefd1f2
It seems the order in which we generated memory accesses changed such that the import of these updated memory accesses failed for the 'loop3' statement in this test case. Unfortunately, the existing CHECK lines were not strict enough to catch this. Hence, besides fixing the order of the memory access lines we also ensure that the memory access changes are both clearly visibly and well checked. llvm-svn: 276247
48 lines
1.5 KiB
Plaintext
48 lines
1.5 KiB
Plaintext
{
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"context" : "[arg] -> { : -9223372036854775808 <= arg <= 9223372036854775807 }",
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"name" : "%loop1---%exit",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "[arg] -> { Stmt_loop1[i0] -> MemRef_A[1 + i0] }"
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}
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],
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"domain" : "[arg] -> { Stmt_loop1[i0] : 0 <= i0 <= -2 + arg }",
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"name" : "Stmt_loop1",
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"schedule" : "[arg] -> { Stmt_loop1[i0] -> [0, i0] }"
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},
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "[arg] -> { Stmt_loop2[i0] -> MemRef_A[1 + i0] }"
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},
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{
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"kind" : "write",
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"relation" : "[arg] -> { Stmt_loop2[i0] -> MemRef_val[] }"
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}
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],
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"domain" : "[arg] -> { Stmt_loop2[i0] : 0 <= i0 <= -2 + arg }",
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"name" : "Stmt_loop2",
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"schedule" : "[arg] -> { Stmt_loop2[i0] -> [1, i0] }"
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},
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_A[1 + i0] }"
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},
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{
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"kind" : "read",
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"relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_val[] }"
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}
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],
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"domain" : "[arg] -> { Stmt_loop3[i0] : 0 <= i0 <= -2 + arg }",
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"name" : "Stmt_loop3",
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"schedule" : "[arg] -> { Stmt_loop3[i0] -> [2, i0] }"
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}
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]
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}
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