a201f8872a
Use a function attribute (amdgpu-dynamic-vgpr) instead of a subtarget feature, as requested in #130030.
323 lines
12 KiB
C++
323 lines
12 KiB
C++
//===--------- llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUUnitTests.h"
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#include "AMDGPUTargetMachine.h"
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#include "GCNSubtarget.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/TargetParser/TargetParser.h"
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#include "gtest/gtest.h"
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#include "AMDGPUGenSubtargetInfo.inc"
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using namespace llvm;
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std::once_flag flag;
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void InitializeAMDGPUTarget() {
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std::call_once(flag, []() {
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LLVMInitializeAMDGPUTargetInfo();
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LLVMInitializeAMDGPUTarget();
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LLVMInitializeAMDGPUTargetMC();
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});
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}
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std::unique_ptr<const GCNTargetMachine>
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llvm::createAMDGPUTargetMachine(std::string TStr, StringRef CPU, StringRef FS) {
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InitializeAMDGPUTarget();
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Triple TT(TStr);
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std::string Error;
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const Target *T = TargetRegistry::lookupTarget(TT, Error);
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if (!T)
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return nullptr;
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TargetOptions Options;
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return std::unique_ptr<GCNTargetMachine>(
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static_cast<GCNTargetMachine *>(T->createTargetMachine(
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TT, CPU, FS, Options, std::nullopt, std::nullopt)));
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}
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static cl::opt<bool> PrintCpuRegLimits(
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"print-cpu-reg-limits", cl::NotHidden, cl::init(false),
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cl::desc("force printing per AMDGPU CPU register limits"));
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static bool checkMinMax(std::stringstream &OS, unsigned Occ, unsigned MinOcc,
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unsigned MaxOcc,
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std::function<unsigned(unsigned)> GetOcc,
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std::function<unsigned(unsigned)> GetMinGPRs,
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std::function<unsigned(unsigned)> GetMaxGPRs) {
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bool MinValid = true, MaxValid = true, RangeValid = true;
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unsigned MinGPRs = GetMinGPRs(Occ);
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unsigned MaxGPRs = GetMaxGPRs(Occ);
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unsigned RealOcc;
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if (MinGPRs >= MaxGPRs)
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RangeValid = false;
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else {
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RealOcc = GetOcc(MinGPRs);
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for (unsigned NumRegs = MinGPRs + 1; NumRegs <= MaxGPRs; ++NumRegs) {
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if (RealOcc != GetOcc(NumRegs)) {
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RangeValid = false;
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break;
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}
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}
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}
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if (RangeValid && RealOcc > MinOcc && RealOcc <= MaxOcc) {
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if (MinGPRs > 0 && GetOcc(MinGPRs - 1) <= RealOcc)
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MinValid = false;
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if (GetOcc(MaxGPRs + 1) >= RealOcc)
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MaxValid = false;
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}
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std::stringstream MinStr;
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MinStr << (MinValid ? ' ' : '<') << ' ' << std::setw(3) << MinGPRs << " (O"
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<< GetOcc(MinGPRs) << ") " << (RangeValid ? ' ' : 'R');
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OS << std::left << std::setw(15) << MinStr.str() << std::setw(3) << MaxGPRs
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<< " (O" << GetOcc(MaxGPRs) << ')' << (MaxValid ? "" : " >");
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return MinValid && MaxValid && RangeValid;
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}
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static const std::pair<StringRef, StringRef>
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EmptyFS = {"", ""},
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W32FS = {"+wavefrontsize32", "w32"},
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W64FS = {"+wavefrontsize64", "w64"};
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using TestFuncTy = function_ref<bool(std::stringstream &, unsigned,
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const GCNSubtarget &, bool)>;
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static bool testAndRecord(std::stringstream &Table, const GCNSubtarget &ST,
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TestFuncTy test, unsigned DynamicVGPRBlockSize) {
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bool Success = true;
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unsigned MaxOcc = ST.getMaxWavesPerEU();
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for (unsigned Occ = MaxOcc; Occ > 0; --Occ) {
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Table << std::right << std::setw(3) << Occ << " ";
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Success = test(Table, Occ, ST, DynamicVGPRBlockSize) && Success;
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Table << '\n';
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}
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return Success;
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}
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static void testGPRLimits(const char *RegName, bool TestW32W64,
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TestFuncTy test) {
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SmallVector<StringRef> CPUs;
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AMDGPU::fillValidArchListAMDGCN(CPUs);
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std::map<std::string, SmallVector<std::string>> TablePerCPUs;
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for (auto CPUName : CPUs) {
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auto CanonCPUName =
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AMDGPU::getArchNameAMDGCN(AMDGPU::parseArchAMDGCN(CPUName));
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auto *FS = &EmptyFS;
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while (true) {
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auto TM = createAMDGPUTargetMachine("amdgcn-amd-", CPUName, FS->first);
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if (!TM)
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break;
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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if (TestW32W64 &&
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ST.getFeatureBits().test(AMDGPU::FeatureWavefrontSize32))
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FS = &W32FS;
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std::stringstream Table;
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bool Success = testAndRecord(Table, ST, test, /*DynamicVGPRBlockSize=*/0);
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if (!Success || PrintCpuRegLimits)
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TablePerCPUs[Table.str()].push_back((CanonCPUName + FS->second).str());
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if (FS != &W32FS)
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break;
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FS = &W64FS;
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}
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}
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std::stringstream OS;
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for (auto &P : TablePerCPUs) {
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for (auto &CPUName : P.second)
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OS << ' ' << CPUName;
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OS << ":\nOcc Min" << RegName << " Max" << RegName << '\n'
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<< P.first << '\n';
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}
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auto ErrStr = OS.str();
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EXPECT_TRUE(ErrStr.empty()) << ErrStr;
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}
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static void testDynamicVGPRLimits(StringRef CPUName, StringRef FS,
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TestFuncTy test) {
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auto TM = createAMDGPUTargetMachine("amdgcn-amd-", CPUName, FS);
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ASSERT_TRUE(TM) << "No target machine";
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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auto testWithBlockSize = [&](unsigned DynamicVGPRBlockSize) {
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std::stringstream Table;
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bool Success = testAndRecord(Table, ST, test, DynamicVGPRBlockSize);
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EXPECT_TRUE(Success && !PrintCpuRegLimits)
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<< CPUName << " dynamic VGPR block size " << DynamicVGPRBlockSize
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<< ":\nOcc MinVGPR MaxVGPR\n"
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<< Table.str() << '\n';
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};
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testWithBlockSize(16);
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testWithBlockSize(32);
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}
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TEST(AMDGPU, TestVGPRLimitsPerOccupancy) {
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auto test = [](std::stringstream &OS, unsigned Occ, const GCNSubtarget &ST,
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unsigned DynamicVGPRBlockSize) {
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unsigned MaxVGPRNum = ST.getAddressableNumVGPRs(DynamicVGPRBlockSize);
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return checkMinMax(
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OS, Occ, ST.getOccupancyWithNumVGPRs(MaxVGPRNum, DynamicVGPRBlockSize),
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ST.getMaxWavesPerEU(),
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[&](unsigned NumGPRs) {
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return ST.getOccupancyWithNumVGPRs(NumGPRs, DynamicVGPRBlockSize);
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},
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[&](unsigned Occ) {
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return ST.getMinNumVGPRs(Occ, DynamicVGPRBlockSize);
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},
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[&](unsigned Occ) {
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return ST.getMaxNumVGPRs(Occ, DynamicVGPRBlockSize);
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});
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};
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testGPRLimits("VGPR", true, test);
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testDynamicVGPRLimits("gfx1200", "+wavefrontsize32", test);
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}
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static void testAbsoluteLimits(StringRef CPUName, StringRef FS,
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unsigned DynamicVGPRBlockSize,
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unsigned ExpectedMinOcc, unsigned ExpectedMaxOcc,
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unsigned ExpectedMaxVGPRs) {
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auto TM = createAMDGPUTargetMachine("amdgcn-amd-", CPUName, FS);
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ASSERT_TRUE(TM) << "No target machine";
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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// Test function without attributes.
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LLVMContext Context;
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Module M("", Context);
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Function *Func =
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Function::Create(FunctionType::get(Type::getVoidTy(Context), false),
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GlobalValue::ExternalLinkage, "testFunc", &M);
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Func->setCallingConv(CallingConv::AMDGPU_CS_Chain);
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Func->addFnAttr("amdgpu-flat-work-group-size", "1,32");
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std::string DVGPRBlockSize = std::to_string(DynamicVGPRBlockSize);
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if (DynamicVGPRBlockSize)
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Func->addFnAttr("amdgpu-dynamic-vgpr-block-size", DVGPRBlockSize);
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auto Range = ST.getWavesPerEU(*Func);
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EXPECT_EQ(ExpectedMinOcc, Range.first) << CPUName << ' ' << FS;
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EXPECT_EQ(ExpectedMaxOcc, Range.second) << CPUName << ' ' << FS;
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EXPECT_EQ(ExpectedMaxVGPRs, ST.getMaxNumVGPRs(*Func)) << CPUName << ' ' << FS;
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EXPECT_EQ(ExpectedMaxVGPRs, ST.getAddressableNumVGPRs(DynamicVGPRBlockSize))
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<< CPUName << ' ' << FS;
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// Function with requested 'amdgpu-waves-per-eu' in a valid range.
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Func->addFnAttr("amdgpu-waves-per-eu", "10,12");
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Range = ST.getWavesPerEU(*Func);
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EXPECT_EQ(10u, Range.first) << CPUName << ' ' << FS;
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EXPECT_EQ(12u, Range.second) << CPUName << ' ' << FS;
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}
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TEST(AMDGPU, TestOccupancyAbsoluteLimits) {
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// CPUName, Features, DynamicVGPRBlockSize; Expected MinOcc, MaxOcc, MaxVGPRs
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testAbsoluteLimits("gfx1200", "+wavefrontsize32", 0, 1, 16, 256);
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testAbsoluteLimits("gfx1200", "+wavefrontsize32", 16, 1, 16, 128);
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testAbsoluteLimits("gfx1200", "+wavefrontsize32", 32, 1, 16, 256);
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}
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static const char *printSubReg(const TargetRegisterInfo &TRI, unsigned SubReg) {
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return SubReg ? TRI.getSubRegIndexName(SubReg) : "<none>";
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}
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TEST(AMDGPU, TestReverseComposeSubRegIndices) {
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auto TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx900", "");
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if (!TM)
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return;
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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#define EXPECT_SUBREG_EQ(A, B, Expect) \
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do { \
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unsigned Reversed = TRI->reverseComposeSubRegIndices(A, B); \
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EXPECT_EQ(Reversed, Expect) \
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<< printSubReg(*TRI, A) << ", " << printSubReg(*TRI, B) << " => " \
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<< printSubReg(*TRI, Reversed) << ", *" << printSubReg(*TRI, Expect); \
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} while (0);
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EXPECT_SUBREG_EQ(AMDGPU::NoSubRegister, AMDGPU::sub0, AMDGPU::sub0);
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EXPECT_SUBREG_EQ(AMDGPU::sub0, AMDGPU::NoSubRegister, AMDGPU::sub0);
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EXPECT_SUBREG_EQ(AMDGPU::sub0, AMDGPU::sub0, AMDGPU::sub0);
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EXPECT_SUBREG_EQ(AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub1);
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EXPECT_SUBREG_EQ(AMDGPU::sub1, AMDGPU::sub0, AMDGPU::NoSubRegister);
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EXPECT_SUBREG_EQ(AMDGPU::sub0_sub1, AMDGPU::sub0, AMDGPU::sub0);
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EXPECT_SUBREG_EQ(AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1);
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EXPECT_SUBREG_EQ(AMDGPU::sub0_sub1_sub2_sub3, AMDGPU::sub0_sub1,
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AMDGPU::sub0_sub1);
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EXPECT_SUBREG_EQ(AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2_sub3,
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AMDGPU::sub0_sub1_sub2_sub3);
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EXPECT_SUBREG_EQ(AMDGPU::sub0_sub1_sub2_sub3, AMDGPU::sub1_sub2,
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AMDGPU::sub1_sub2);
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EXPECT_SUBREG_EQ(AMDGPU::sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3,
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AMDGPU::NoSubRegister);
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EXPECT_SUBREG_EQ(AMDGPU::sub1_sub2_sub3, AMDGPU::sub0_sub1_sub2_sub3,
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AMDGPU::NoSubRegister);
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EXPECT_SUBREG_EQ(AMDGPU::sub0_sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3,
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AMDGPU::sub1_sub2_sub3);
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EXPECT_SUBREG_EQ(AMDGPU::sub0, AMDGPU::sub30, AMDGPU::NoSubRegister);
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EXPECT_SUBREG_EQ(AMDGPU::sub30, AMDGPU::sub0, AMDGPU::NoSubRegister);
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EXPECT_SUBREG_EQ(AMDGPU::sub0, AMDGPU::sub31, AMDGPU::NoSubRegister);
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EXPECT_SUBREG_EQ(AMDGPU::sub31, AMDGPU::sub0, AMDGPU::NoSubRegister);
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EXPECT_SUBREG_EQ(AMDGPU::sub0_sub1, AMDGPU::sub30, AMDGPU::NoSubRegister);
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EXPECT_SUBREG_EQ(AMDGPU::sub30, AMDGPU::sub0_sub1, AMDGPU::NoSubRegister);
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EXPECT_SUBREG_EQ(AMDGPU::sub0_sub1, AMDGPU::sub30_sub31,
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AMDGPU::NoSubRegister);
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EXPECT_SUBREG_EQ(AMDGPU::sub30_sub31, AMDGPU::sub0_sub1,
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AMDGPU::NoSubRegister);
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for (unsigned SubIdx0 = 1, LastSubReg = TRI->getNumSubRegIndices();
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SubIdx0 != LastSubReg; ++SubIdx0) {
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for (unsigned SubIdx1 = 1; SubIdx1 != LastSubReg; ++SubIdx1) {
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if (unsigned ForwardCompose =
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TRI->composeSubRegIndices(SubIdx0, SubIdx1)) {
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unsigned ReverseComposed =
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TRI->reverseComposeSubRegIndices(SubIdx0, ForwardCompose);
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EXPECT_EQ(ReverseComposed, SubIdx1);
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}
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if (unsigned ReverseCompose =
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TRI->reverseComposeSubRegIndices(SubIdx0, SubIdx1)) {
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unsigned Recompose = TRI->composeSubRegIndices(SubIdx0, ReverseCompose);
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EXPECT_EQ(Recompose, SubIdx1);
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}
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}
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}
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}
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