a65ccc1b9f
On processors supporting vector registers and SIMD instructions, enable i128 as legal type in VRs. This allows many operations to be implemented via native instructions directly in VRs (including add, subtract, logical operations and shifts). For a few other operations (e.g. multiply and divide, as well as atomic operations), we need to move the i128 value back to a GPR pair to use the corresponding instruction there. Overall, this is still beneficial. The patch includes the following LLVM changes: - Enable i128 as legal type - Set up legal operations (in SystemZInstrVector.td) - Custom expansion for i128 add/subtract with carry - Custom expansion for i128 comparisons and selects - Support for moving i128 to/from GPR pairs when required - Handle 128-bit integer constant values everywhere - Use i128 as intrinsic operand type where appropriate - Updated and new test cases In addition, clang builtins are updated to reflect the intrinsic operand type changes (which also improves compatibility with GCC).
170 lines
4.2 KiB
LLVM
170 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Test removal of AND operations that don't affect last 6 bits of shift amount
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; operand.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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; Test that AND is not removed when some lower 6 bits are not set.
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define i32 @f1(i32 %a, i32 %sh) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nill %r3, 31
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; CHECK-NEXT: sll %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 31
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask with only bottom 6 bits set.
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define i32 @f2(i32 %a, i32 %sh) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 63
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask including but not limited to bottom 6 bits.
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define i32 @f3(i32 %a, i32 %sh) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 255
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask from SRA.
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define i32 @f4(i32 %a, i32 %sh) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sra %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 63
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%shift = ashr i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask from SRL.
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define i32 @f5(i32 %a, i32 %sh) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srl %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 63
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%shift = lshr i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask from SLLG.
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define i64 @f6(i64 %a, i64 %sh) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sllg %r2, %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i64 %sh, 63
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%shift = shl i64 %a, %and
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ret i64 %shift
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}
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; Test removal of AND mask from SRAG.
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define i64 @f7(i64 %a, i64 %sh) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srag %r2, %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i64 %sh, 63
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%shift = ashr i64 %a, %and
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ret i64 %shift
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}
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; Test removal of AND mask from SRLG.
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define i64 @f8(i64 %a, i64 %sh) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srlg %r2, %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i64 %sh, 63
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%shift = lshr i64 %a, %and
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ret i64 %shift
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}
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; Test that AND with two register operands is not affected.
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define i32 @f9(i32 %a, i32 %b, i32 %sh) {
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; CHECK-LABEL: f9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nr %r3, %r4
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; CHECK-NEXT: sll %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, %b
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test that AND is not entirely removed if the result is reused.
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define i32 @f10(i32 %a, i32 %sh) {
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; CHECK-LABEL: f10:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll %r2, 0(%r3)
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; CHECK-NEXT: nilf %r3, 63
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; CHECK-NEXT: ar %r2, %r3
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 63
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%shift = shl i32 %a, %and
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%reuse = add i32 %and, %shift
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ret i32 %reuse
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}
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define i128 @f11(i128 %a, i32 %sh) {
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; CHECK-LABEL: f11:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vlvgp %v1, %r4, %r4
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vslb %v0, %v0, %v1
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; CHECK-NEXT: vsl %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 127
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%ext = zext i32 %and to i128
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%shift = shl i128 %a, %ext
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ret i128 %shift
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}
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define i128 @f12(i128 %a, i32 %sh) {
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; CHECK-LABEL: f12:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vlvgp %v1, %r4, %r4
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrlb %v0, %v0, %v1
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; CHECK-NEXT: vsrl %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 127
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%ext = zext i32 %and to i128
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%shift = lshr i128 %a, %ext
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ret i128 %shift
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}
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define i128 @f13(i128 %a, i32 %sh) {
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; CHECK-LABEL: f13:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vlvgp %v1, %r4, %r4
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrab %v0, %v0, %v1
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; CHECK-NEXT: vsra %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 127
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%ext = zext i32 %and to i128
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%shift = ashr i128 %a, %ext
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ret i128 %shift
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}
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