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clang-p2996/llvm/lib/Target/RISCV
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Craig Topper 40b230f685 [RISCV] Limit transformAddImmMulImm to prevent an infinite loop. 
This fixes an issue reported in D108607.
2021-09-23 15:53:11 -07:00
..
AsmParser
[RISCV] Rename prefix FeatureExt* to FeatureStdExt* for all sub-extension
2021-09-13 16:24:15 +08:00
Disassembler
[RISCV] Rename prefix FeatureExt* to FeatureStdExt* for all sub-extension
2021-09-13 16:24:15 +08:00
MCTargetDesc
[RISCV] Rename prefix FeatureExt* to FeatureStdExt* for all sub-extension
2021-09-13 16:24:15 +08:00
TargetInfo
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CMakeLists.txt
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
RISCV.h
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
RISCV.td
[RISCV] Rename prefix FeatureExt* to FeatureStdExt* for all sub-extension
2021-09-13 16:24:15 +08:00
RISCVAsmPrinter.cpp
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RISCVCallingConv.td
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
[RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos
2021-09-08 09:23:33 -07:00
RISCVFrameLowering.cpp
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
RISCVFrameLowering.h
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
RISCVGatherScatterLowering.cpp
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Teach vsetvli insertion that stores don't use the policy bits in vtype.
2021-09-10 09:03:20 -07:00
RISCVInstrFormats.td
[RISCV] Initial support .insn directive for the assembler.
2021-09-12 15:56:12 -07:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
[RISCV] Add missing op type OPERAND_UIMM2, OPERAND_UIMM3 and OPERAND_UIMM7 for verifyInstruction
2021-09-23 19:30:46 +08:00
RISCVInstrInfo.h
[TII] Remove the MFI argument to convertToThreeAddress. NFC.
2021-09-23 08:58:46 +01:00
RISCVInstrInfo.td
[RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used.
2021-09-16 11:03:35 -07:00
RISCVInstrInfoA.td
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RISCVInstrInfoB.td
[RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64.
2021-08-26 10:20:19 -07:00
RISCVInstrInfoC.td
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RISCVInstrInfoD.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstrInfoF.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstrInfoM.td
[RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used.
2021-09-16 11:03:35 -07:00
RISCVInstrInfoV.td
[RISCV] Remove unused tablegen template parameters. NFC
2021-09-08 10:01:42 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove unused tablegen template parameters. NFC
2021-09-08 10:01:42 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Remove unused tablegen template parameters. NFC
2021-09-08 10:01:42 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV][VP] Add support for VP_REDUCE_* operations
2021-09-23 11:11:05 +01:00
RISCVInstrInfoZfh.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstructionSelector.cpp
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RISCVISelDAGToDAG.cpp
[RISCV] Add another isel optimization for (and (shl x, c2), c1)
2021-09-23 14:18:07 -07:00
RISCVISelDAGToDAG.h
[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
2021-08-18 11:07:11 -07:00
RISCVISelLowering.cpp
[RISCV] Limit transformAddImmMulImm to prevent an infinite loop.
2021-09-23 15:53:11 -07:00
RISCVISelLowering.h
[RISCV][VP] Add support for VP_REDUCE_* operations
2021-09-23 11:11:05 +01:00
RISCVLegalizerInfo.cpp
[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.h
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RISCVMCInstLower.cpp
[RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions.
2021-08-04 10:39:50 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Indicate that RISCVMergeBaseOffsetOpt preserves the CFG.
2021-08-03 08:32:36 -07:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] Reserve an emergency spill slot for any RVV spills
2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
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RISCVRegisterInfo.td
[RISCV] Initial support .insn directive for the assembler.
2021-09-12 15:56:12 -07:00
RISCVSchedRocket.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSchedSiFive7.td
[RISCV] Fix typo in RISCVSchedSiFive7.td
2021-09-01 16:39:48 -05:00
RISCVSchedule.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVScheduleB.td
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RISCVScheduleV.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSubtarget.cpp
[RISCV] Add -riscv-v-fixed-length-vector-elen-max to limit the ELEN used for fixed length vectorization.
2021-08-27 10:17:35 -07:00
RISCVSubtarget.h
[RISCV] Add -riscv-v-fixed-length-vector-elen-max to limit the ELEN used for fixed length vectorization.
2021-08-27 10:17:35 -07:00
RISCVSystemOperands.td
RISCV: add a few deprecated aliases for CSRs
2021-05-21 13:52:58 -07:00
RISCVTargetMachine.cpp
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[RISCV] Add zext.h/zext.w to RISCVTTIImpl::getIntImmCostInst.
2021-08-18 09:40:40 -07:00
RISCVTargetTransformInfo.h
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00