1e3c6fc7cb
This is basically D108837 but for jump threading. Free instructions should be ignored for the threading decision. JumpThreading already skips some free instructions (like pointer bitcasts), but does not skip various free intrinsics -- in fact, it currently gives them a fairly large cost of 2. Differential Revision: https://reviews.llvm.org/D110290
92 lines
3.6 KiB
LLVM
92 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -O2 -preserve-alignment-assumptions-during-inlining=0 < %s | FileCheck %s --check-prefixes=CHECK,ASSUMPTIONS-OFF
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; RUN: opt -S -O2 -preserve-alignment-assumptions-during-inlining=1 < %s | FileCheck %s --check-prefixes=CHECK,ASSUMPTIONS-ON
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; RUN: opt -S -O2 < %s | FileCheck %s --check-prefixes=CHECK,ASSUMPTIONS-OFF
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target datalayout = "e-p:64:64-p5:32:32-A5"
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; This illustrates an optimization difference caused by instruction counting
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; heuristics, which are affected by the additional instructions of the
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; alignment assumption.
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define internal i1 @callee1(i1 %c, i64* align 8 %ptr) {
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store volatile i64 0, i64* %ptr
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ret i1 %c
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}
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define void @caller1(i1 %c, i64* align 1 %ptr) {
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; ASSUMPTIONS-OFF-LABEL: @caller1(
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; ASSUMPTIONS-OFF-NEXT: br i1 [[C:%.*]], label [[COMMON_RET:%.*]], label [[FALSE2:%.*]]
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; ASSUMPTIONS-OFF: common.ret:
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; ASSUMPTIONS-OFF-NEXT: [[DOTSINK:%.*]] = phi i64 [ 3, [[FALSE2]] ], [ 2, [[TMP0:%.*]] ]
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 0, i64* [[PTR:%.*]], align 8
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 [[DOTSINK]], i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: ret void
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; ASSUMPTIONS-OFF: false2:
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: br label [[COMMON_RET]]
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;
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; ASSUMPTIONS-ON-LABEL: @caller1(
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; ASSUMPTIONS-ON-NEXT: br i1 [[C:%.*]], label [[COMMON_RET:%.*]], label [[FALSE2:%.*]]
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; ASSUMPTIONS-ON: common.ret:
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; ASSUMPTIONS-ON-NEXT: [[DOTSINK:%.*]] = phi i64 [ 3, [[FALSE2]] ], [ 2, [[TMP0:%.*]] ]
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; ASSUMPTIONS-ON-NEXT: call void @llvm.assume(i1 true) [ "align"(i64* [[PTR:%.*]], i64 8) ]
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; ASSUMPTIONS-ON-NEXT: store volatile i64 0, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 [[DOTSINK]], i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: ret void
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; ASSUMPTIONS-ON: false2:
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; ASSUMPTIONS-ON-NEXT: store volatile i64 1, i64* [[PTR]], align 4
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; ASSUMPTIONS-ON-NEXT: br label [[COMMON_RET]]
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;
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br i1 %c, label %true1, label %false1
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true1:
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%c2 = call i1 @callee1(i1 %c, i64* %ptr)
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store volatile i64 -1, i64* %ptr
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store volatile i64 -1, i64* %ptr
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store volatile i64 -1, i64* %ptr
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store volatile i64 -1, i64* %ptr
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store volatile i64 -1, i64* %ptr
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br i1 %c2, label %true2, label %false2
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false1:
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store volatile i64 1, i64* %ptr
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br label %true1
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true2:
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store volatile i64 2, i64* %ptr
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ret void
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false2:
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store volatile i64 3, i64* %ptr
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ret void
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}
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; This test checks that alignment assumptions do not prevent SROA.
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; See PR45763.
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define internal void @callee2(i64* noalias sret(i64) align 32 %arg) {
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store i64 0, i64* %arg, align 8
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ret void
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}
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define amdgpu_kernel void @caller2() {
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; CHECK-LABEL: @caller2(
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; CHECK-NEXT: ret void
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;
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%alloca = alloca i64, align 8, addrspace(5)
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%cast = addrspacecast i64 addrspace(5)* %alloca to i64*
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call void @callee2(i64* sret(i64) align 32 %cast)
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ret void
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}
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