Andrei Safronov a2c9f7dbcc [Xtensa] Implement lowering SELECT_CC/BRCC for Xtensa FP Option. (#145544) ...

Also minor format changes in disassembler test for Xtensa FP Option.

2025-07-02 13:48:49 +03:00

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Analysis

[AArch64][TTI] Reduce cost for splatting whole first vector segment (SVE) (#145701)

2025-07-02 09:51:56 +01:00

Assembler

[AArch64] Mark neon.stN intrinsics as writeonly (#145289)

2025-07-01 15:56:02 +02:00

Bindings

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Bitcode

[IR] Introduce dead_on_return attribute

2025-07-02 09:29:36 +02:00

BugPoint

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CodeGen

[Xtensa] Implement lowering SELECT_CC/BRCC for Xtensa FP Option. (#145544)

2025-07-02 13:48:49 +03:00

DebugInfo

[KeyInstr] Fully support mixed key/non-key inlining modes (#144103)

2025-06-30 09:56:56 +01:00

Demangle

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Examples

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ExecutionEngine

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Feature

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FileCheck

[FileCheck] Improve printing variables with escapes (#145865)

2025-06-27 22:39:07 +02:00

Frontend/HLSL

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Instrumentation

[AArch64] Fix stale +zcm target feature to +zcm-gpr64 (#146260)

2025-06-29 15:01:05 +03:00

Integer

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JitListener

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Linker

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LTO

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MachineVerifier

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MC

[Xtensa] Implement lowering SELECT_CC/BRCC for Xtensa FP Option. (#145544)

2025-07-02 13:48:49 +03:00

Object

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ObjectYAML

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Other

[FatLTO] Disable analysis verification in pipeline test (NFC)

2025-07-01 10:47:23 +02:00

SafepointIRVerifier

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Support

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SymbolRewriter

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TableGen

[LLVM][TableGen][DecoderEmitter] Add wrapper struct for bit_value_t (#146248)

2025-07-01 07:36:17 -07:00

ThinLTO

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tools

[AArch64] Change IssueWidth to 5 in AArch64SchedNeoverseN2.td (#145717)

2025-06-30 17:12:02 +01:00

Transforms

[VPlan] Emit VPVectorEndPointerRecipe for reverse interleave pointer adjustment (#144864)

2025-07-02 18:16:02 +08:00

Unit

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Verifier

[IR] Introduce dead_on_return attribute

2025-07-02 09:29:36 +02:00

YAMLParser

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.clang-format

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CMakeLists.txt

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lit.cfg.py

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lit.site.cfg.py.in

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TestRunner.sh

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