bc6d07ca46
This has been a very painful missing feature that has made producing reduced testcases difficult. In particular the various registers determined for stack access during function lowering were necessary to avoid undefined register errors in a large percentage of cases. Implement a subset of the important fields that need to be preserved for AMDGPU. Most of the changes are to support targets parsing register fields and properly reporting errors. The biggest sort-of bug remaining is for fields that can be initialized from the IR section will be overwritten by a default initialized machineFunctionInfo section. Another remaining bug is the machineFunctionInfo section is still printed even if empty. llvm-svn: 356215
288 lines
11 KiB
YAML
288 lines
11 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-vgpr-index-mode -run-pass=greedy -stress-regalloc=16 -o - %s | FileCheck -check-prefixes=GCN %s
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# An interval for a register that was partially defined was split, creating
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# a new use (a COPY) which was reached by the undef point. In particular,
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# there was a subrange of the new register which was reached by an "undef"
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# point. When the code in extendSegmentsToUses verified value numbers between
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# the new and the old live ranges, it did not account for this kind of a
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# situation and asserted expecting the old value to exist. For a PHI node
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# it is legal to have a missing predecessor value as long as the end of
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# the predecessor is jointly dominated by the undefs.
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#
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# A simplified form of this can be illustrated as
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#
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# bb.1:
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# %0:vreg_64 = IMPLICIT_DEF
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# ...
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# S_CBRANCH_SCC1 %bb.2, implicit $vcc
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# S_BRANCH %bb.3
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#
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# bb.2:
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# ; predecessors: %bb.1, %bb.4
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# dead %1:vreg_64 = COPY %0:vreg_64 ; This is the point of the inserted split
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# ...
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# S_BRANCH %bb.5
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#
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# bb.3:
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# ; predecessors: %bb.1
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# undef %0.sub0:vreg_64 = COPY %123:sreg_32 ; undef point for %0.sub1
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# ...
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# S_BRANCH %bb.4
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#
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# bb.4
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# ; predecessors: %bb.4
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# ...
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# S_BRANCH %bb.2
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#
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# This test exposes this scenario which caused previously caused an assert
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---
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name: _amdgpu_ps_main
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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frameOffsetReg: $sgpr5
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stackPtrOffsetReg: $sgpr32
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liveins:
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- { reg: '$vgpr2', virtual-reg: '%0' }
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- { reg: '$vgpr3', virtual-reg: '%1' }
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- { reg: '$vgpr4', virtual-reg: '%2' }
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body: |
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bb.0:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $vgpr2, $vgpr3, $vgpr4
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%2:vgpr_32 = COPY $vgpr4
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%1:vgpr_32 = COPY $vgpr3
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%0:vgpr_32 = COPY $vgpr2
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S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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bb.1:
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successors: %bb.5(0x80000000)
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undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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%3.sub1:vreg_128 = COPY %3.sub0
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%3.sub2:vreg_128 = COPY %3.sub0
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S_BRANCH %bb.5
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bb.2:
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successors: %bb.3(0x40000000), %bb.4(0x40000000)
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S_CBRANCH_SCC0 %bb.4, implicit undef $scc
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bb.3:
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successors: %bb.5(0x80000000)
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undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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%3.sub1:vreg_128 = COPY %3.sub0
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S_BRANCH %bb.5
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bb.4:
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successors: %bb.5(0x80000000)
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%3:vreg_128 = IMPLICIT_DEF
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bb.5:
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successors: %bb.6(0x40000000), %bb.22(0x40000000)
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%4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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S_CBRANCH_SCC1 %bb.22, implicit undef $scc
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S_BRANCH %bb.6
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bb.6:
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successors: %bb.8(0x40000000), %bb.11(0x40000000)
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%5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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dead %6:vgpr_32 = V_MUL_F32_e32 0, undef %7:vgpr_32, implicit $exec
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dead %8:vgpr_32 = V_MUL_F32_e32 0, %2, implicit $exec
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undef %9.sub1:vreg_64 = V_MUL_F32_e32 0, %1, implicit $exec
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undef %10.sub0:vreg_128 = V_MUL_F32_e32 0, %0, implicit $exec
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undef %11.sub0:sreg_256 = S_MOV_B32 0
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%11.sub1:sreg_256 = COPY %11.sub0
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%11.sub2:sreg_256 = COPY %11.sub0
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%11.sub3:sreg_256 = COPY %11.sub0
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%11.sub4:sreg_256 = COPY %11.sub0
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%11.sub5:sreg_256 = COPY %11.sub0
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%11.sub6:sreg_256 = COPY %11.sub0
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%11.sub7:sreg_256 = COPY %11.sub0
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%12:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %9, %11, undef %13:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
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%14:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
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%15:vreg_128 = IMPLICIT_DEF
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S_CBRANCH_SCC1 %bb.8, implicit undef $scc
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S_BRANCH %bb.11
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bb.7:
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successors: %bb.13(0x80000000)
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; In reality we are checking that this code doesn't assert when splitting
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; and inserting a spill. Here we just check that the point where the error
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; occurs we see a correctly generated spill.
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; GCN-LABEL: bb.7:
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; GCN: SI_SPILL_V128_SAVE %{{[0-9]+}}, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec
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undef %15.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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%15.sub1:vreg_128 = COPY %15.sub0
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%15.sub2:vreg_128 = COPY %15.sub0
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%5:vgpr_32 = IMPLICIT_DEF
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S_BRANCH %bb.13
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bb.8:
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successors: %bb.9(0x40000000), %bb.10(0x40000000)
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S_CBRANCH_SCC0 %bb.10, implicit undef $scc
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bb.9:
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successors: %bb.12(0x80000000)
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; GCN-LABEL: bb.9:
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; GCN: SI_SPILL_V128_SAVE %{{[0-9]+}}, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec
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undef %15.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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%15.sub1:vreg_128 = COPY %15.sub0
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%15.sub2:vreg_128 = COPY %15.sub0
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S_BRANCH %bb.12
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bb.10:
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successors: %bb.12(0x80000000)
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; GCN-LABEL: bb.10:
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; GCN: SI_SPILL_V128_SAVE %{{[0-9]+}}, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec
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undef %15.sub0:vreg_128 = V_MOV_B32_e32 2143289344, implicit $exec
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%15.sub1:vreg_128 = COPY %15.sub0
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%15.sub2:vreg_128 = COPY %15.sub0
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S_BRANCH %bb.12
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bb.11:
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successors: %bb.7(0x40000000), %bb.13(0x40000000)
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%16:sreg_64 = V_CMP_NE_U32_e64 0, %14, implicit $exec
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%17:sreg_64 = S_AND_B64 $exec, %16, implicit-def dead $scc
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$vcc = COPY %17
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S_CBRANCH_VCCNZ %bb.7, implicit $vcc
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S_BRANCH %bb.13
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bb.12:
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successors: %bb.11(0x80000000)
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%14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%5:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
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S_BRANCH %bb.11
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bb.13:
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successors: %bb.15(0x40000000), %bb.14(0x40000000)
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%18:vgpr_32 = V_MAD_F32 0, %10.sub0, 0, target-flags(amdgpu-gotprel) 1073741824, 0, -1082130432, 0, 0, implicit $exec
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%19:vgpr_32 = V_MAD_F32 0, %12.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec
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%20:sreg_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %21:sreg_128, 1040, 0 :: (dereferenceable invariant load 16)
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%22:vgpr_32 = V_ADD_F32_e32 0, %19, implicit $exec
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%23:vgpr_32 = V_MAD_F32 0, %18, 0, 0, 0, 0, 0, 0, implicit $exec
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%24:vgpr_32 = COPY %20.sub3
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%25:vgpr_32 = V_MUL_F32_e64 0, target-flags(amdgpu-gotprel32-lo) 0, 0, %20.sub1, 0, 0, implicit $exec
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%26:sreg_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %27:sreg_128, 1056, 0 :: (dereferenceable invariant load 16)
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%28:vgpr_32 = V_MAD_F32 0, %18, 0, %26.sub0, 0, 0, 0, 0, implicit $exec
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%29:vgpr_32 = V_ADD_F32_e32 %28, %19, implicit $exec
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%30:vgpr_32 = V_RCP_F32_e32 %29, implicit $exec
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%25:vgpr_32 = V_MAC_F32_e32 0, %18, %25, implicit $exec
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%31:vgpr_32 = V_MAD_F32 0, target-flags(amdgpu-gotprel) 0, 0, %12.sub0, 0, %24, 0, 0, implicit $exec
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%32:vgpr_32 = V_ADD_F32_e32 %25, %31, implicit $exec
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%33:vgpr_32 = V_MUL_F32_e32 %22, %30, implicit $exec
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%34:vgpr_32 = V_MUL_F32_e32 %23, %30, implicit $exec
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%35:vgpr_32 = V_MUL_F32_e32 %32, %30, implicit $exec
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%36:vgpr_32 = V_MUL_F32_e32 0, %34, implicit $exec
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%36:vgpr_32 = V_MAC_F32_e32 0, %33, %36, implicit $exec
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%37:vgpr_32 = V_MAD_F32 0, %35, 0, 0, 0, 0, 0, 0, implicit $exec
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%38:sreg_64_xexec = V_CMP_NE_U32_e64 0, %5, implicit $exec
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%39:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %38, implicit $exec
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V_CMP_NE_U32_e32 1, %39, implicit-def $vcc, implicit $exec
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$vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
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%40:vgpr_32 = V_ADD_F32_e32 %36, %37, implicit $exec
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S_CBRANCH_VCCZ %bb.15, implicit $vcc
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bb.14:
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successors: %bb.17(0x80000000)
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S_BRANCH %bb.17
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bb.15:
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successors: %bb.16(0x40000000), %bb.18(0x40000000)
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%41:vgpr_32 = V_MAD_F32 0, %40, 0, 0, 0, 0, 0, 0, implicit $exec
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%42:sreg_64 = V_CMP_LE_F32_e64 0, 0, 0, %41, 0, implicit $exec
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%43:sreg_64 = V_CMP_GE_F32_e64 0, 1065353216, 0, %41, 0, implicit $exec
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%44:sreg_64 = S_AND_B64 %43, %43, implicit-def dead $scc
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%45:sreg_64 = S_AND_B64 %42, %42, implicit-def dead $scc
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%46:sreg_64 = S_AND_B64 %45, %44, implicit-def dead $scc
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%47:sreg_64 = COPY $exec, implicit-def $exec
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%48:sreg_64 = S_AND_B64 %47, %46, implicit-def dead $scc
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$exec = S_MOV_B64_term %48
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SI_MASK_BRANCH %bb.18, implicit $exec
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S_BRANCH %bb.16
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bb.16:
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successors: %bb.18(0x80000000)
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S_BRANCH %bb.18
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bb.17:
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successors: %bb.21(0x40000000), %bb.23(0x40000000)
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%49:sreg_64 = V_CMP_NE_U32_e64 0, %5, implicit $exec
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%50:sreg_64 = S_AND_B64 $exec, %49, implicit-def dead $scc
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%51:vreg_128 = IMPLICIT_DEF
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$vcc = COPY %50
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S_CBRANCH_VCCNZ %bb.21, implicit $vcc
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S_BRANCH %bb.23
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bb.18:
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successors: %bb.20(0x40000000), %bb.19(0x40000000)
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$exec = S_OR_B64 $exec, %47, implicit-def $scc
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%52:vgpr_32 = V_MAD_F32 0, %3.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 1, %3.sub0, 0, 0, implicit $exec
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%53:vgpr_32 = V_MUL_F32_e32 -2147483648, %3.sub1, implicit $exec
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%53:vgpr_32 = V_MAC_F32_e32 target-flags(amdgpu-gotprel32-hi) 1065353216, %3.sub2, %53, implicit $exec
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%54:vgpr_32 = V_MUL_F32_e32 %53, %53, implicit $exec
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%54:vgpr_32 = V_MAC_F32_e32 %52, %52, %54, implicit $exec
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%55:vgpr_32 = V_SQRT_F32_e32 %54, implicit $exec
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%5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%56:vgpr_32 = V_MOV_B32_e32 981668463, implicit $exec
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%57:sreg_64 = V_CMP_NGT_F32_e64 0, %55, 0, %56, 0, implicit $exec
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%58:sreg_64 = S_AND_B64 $exec, %57, implicit-def dead $scc
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$vcc = COPY %58
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S_CBRANCH_VCCZ %bb.20, implicit $vcc
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bb.19:
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successors: %bb.17(0x80000000)
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S_BRANCH %bb.17
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bb.20:
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successors: %bb.17(0x80000000)
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S_BRANCH %bb.17
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bb.21:
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successors: %bb.23(0x80000000)
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%59:sreg_32 = S_MOV_B32 0
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undef %51.sub0:vreg_128 = COPY %59
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S_BRANCH %bb.23
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bb.22:
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successors: %bb.24(0x80000000)
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S_BRANCH %bb.24
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bb.23:
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successors: %bb.22(0x80000000)
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undef %60.sub1:vreg_64 = V_CVT_I32_F32_e32 %1, implicit $exec
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%60.sub0:vreg_64 = V_CVT_I32_F32_e32 %0, implicit $exec
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undef %61.sub0:sreg_256 = S_MOV_B32 0
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%61.sub1:sreg_256 = COPY %61.sub0
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%61.sub2:sreg_256 = COPY %61.sub0
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%61.sub3:sreg_256 = COPY %61.sub0
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%61.sub4:sreg_256 = COPY %61.sub0
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%61.sub5:sreg_256 = COPY %61.sub0
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%61.sub6:sreg_256 = COPY %61.sub0
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%61.sub7:sreg_256 = COPY %61.sub0
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%62:vgpr_32 = V_MOV_B32_e32 1033100696, implicit $exec
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%63:vgpr_32 = V_MUL_F32_e32 1060575065, %15.sub1, implicit $exec
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%63:vgpr_32 = V_MAC_F32_e32 1046066128, %15.sub0, %63, implicit $exec
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%64:vgpr_32 = IMAGE_LOAD_V1_V2 %60, %61, 1, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
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%64:vgpr_32 = V_MAC_F32_e32 target-flags(amdgpu-gotprel) 0, %51.sub0, %64, implicit $exec
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%65:vgpr_32 = V_MUL_F32_e32 0, %64, implicit $exec
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%66:vgpr_32 = V_MUL_F32_e32 0, %65, implicit $exec
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%67:vgpr_32 = V_MAD_F32 0, %66, 0, %62, 0, 0, 0, 0, implicit $exec
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%63:vgpr_32 = V_MAC_F32_e32 %15.sub2, %62, %63, implicit $exec
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%4:vgpr_32 = V_ADD_F32_e32 %63, %67, implicit $exec
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S_BRANCH %bb.22
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bb.24:
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%68:vgpr_32 = V_MUL_F32_e32 0, %4, implicit $exec
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%69:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, undef %70:vgpr_32, 0, %68, 0, 0, implicit $exec
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EXP 0, undef %71:vgpr_32, %69, undef %72:vgpr_32, undef %73:vgpr_32, -1, -1, 15, implicit $exec
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S_ENDPGM 0
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...
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