a576281694
than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
232 lines
8.6 KiB
C++
232 lines
8.6 KiB
C++
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Mips target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsTargetMachine.h"
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#include "Mips.h"
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#include "Mips16FrameLowering.h"
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#include "Mips16HardFloat.h"
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#include "Mips16ISelDAGToDAG.h"
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#include "Mips16ISelLowering.h"
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#include "Mips16InstrInfo.h"
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#include "MipsFrameLowering.h"
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#include "MipsInstrInfo.h"
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#include "MipsModuleISelDAGToDAG.h"
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#include "MipsOs16.h"
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#include "MipsSEFrameLowering.h"
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#include "MipsSEISelDAGToDAG.h"
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#include "MipsSEISelLowering.h"
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#include "MipsSEInstrInfo.h"
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#include "MipsTargetObjectFile.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips"
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extern "C" void LLVMInitializeMipsTarget() {
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// Register the target.
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RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
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RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
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RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
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RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
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}
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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// offset from the stack/frame pointer, using StackGrowsUp enables
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// an easier handling.
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// Using CodeModel::Large enables different CALL behavior.
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MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
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ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)),
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Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
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NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
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isLittle, *this),
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Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
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isLittle, *this) {
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Subtarget = &DefaultSubtarget;
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initAsmInfo();
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}
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MipsTargetMachine::~MipsTargetMachine() {}
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void MipsebTargetMachine::anchor() { }
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MipsebTargetMachine::
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MipsebTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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void MipselTargetMachine::anchor() { }
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MipselTargetMachine::
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MipselTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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const MipsSubtarget *
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MipsTargetMachine::getSubtargetImpl(const Function &F) const {
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AttributeSet FnAttrs = F.getAttributes();
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Attribute CPUAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
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Attribute FSAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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bool hasMips16Attr =
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!FnAttrs.getAttribute(AttributeSet::FunctionIndex, "mips16")
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.hasAttribute(Attribute::None);
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bool hasNoMips16Attr =
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!FnAttrs.getAttribute(AttributeSet::FunctionIndex, "nomips16")
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.hasAttribute(Attribute::None);
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// FIXME: This is related to the code below to reset the target options,
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// we need to know whether or not the soft float flag is set on the
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// function before we can generate a subtarget. We also need to use
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// it as a key for the subtarget since that can be the only difference
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// between two functions.
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Attribute SFAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");
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bool softFloat = !SFAttr.hasAttribute(Attribute::None)
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? SFAttr.getValueAsString() == "true"
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: Options.UseSoftFloat;
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if (hasMips16Attr)
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FS += FS.empty() ? "+mips16" : ",+mips16";
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else if (hasNoMips16Attr)
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FS += FS.empty() ? "-mips16" : ",-mips16";
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auto &I = SubtargetMap[CPU + FS + (softFloat ? "use-soft-float=true"
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: "use-soft-float=false")];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this);
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}
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return I.get();
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}
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void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
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DEBUG(dbgs() << "resetSubtarget\n");
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Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
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MF->setSubtarget(Subtarget);
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return;
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}
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namespace {
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/// Mips Code Generator Pass Configuration Options.
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class MipsPassConfig : public TargetPassConfig {
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public:
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MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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// The current implementation of long branch pass requires a scratch
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// register ($at) to be available before branch instructions. Tail merging
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// can break this requirement, so disable it when long branch pass is
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// enabled.
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EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
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}
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MipsTargetMachine &getMipsTargetMachine() const {
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return getTM<MipsTargetMachine>();
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}
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const MipsSubtarget &getMipsSubtarget() const {
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return *getMipsTargetMachine().getSubtargetImpl();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addMachineSSAOptimization() override;
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void addPreEmitPass() override;
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void addPreRegAlloc() override;
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};
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} // namespace
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TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new MipsPassConfig(this, PM);
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}
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void MipsPassConfig::addIRPasses() {
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TargetPassConfig::addIRPasses();
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addPass(createAtomicExpandPass(&getMipsTargetMachine()));
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if (getMipsSubtarget().os16())
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addPass(createMipsOs16(getMipsTargetMachine()));
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if (getMipsSubtarget().inMips16HardFloat())
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addPass(createMips16HardFloat(getMipsTargetMachine()));
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}
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsPassConfig::addInstSelector() {
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addPass(createMipsModuleISelDag(getMipsTargetMachine()));
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addPass(createMips16ISelDag(getMipsTargetMachine()));
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addPass(createMipsSEISelDag(getMipsTargetMachine()));
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return false;
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}
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void MipsPassConfig::addMachineSSAOptimization() {
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addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
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TargetPassConfig::addMachineSSAOptimization();
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}
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void MipsPassConfig::addPreRegAlloc() {
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if (getOptLevel() == CodeGenOpt::None)
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addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
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}
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void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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if (Subtarget->allowMixed16_32()) {
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DEBUG(errs() << "No ");
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//FIXME: The Basic Target Transform Info
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// pass needs to become a function pass instead of
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// being an immutable pass and then this method as it exists now
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// would be unnecessary.
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PM.add(createNoTargetTransformInfoPass());
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} else
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LLVMTargetMachine::addAnalysisPasses(PM);
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DEBUG(errs() << "Target Transform Info Pass Added\n");
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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void MipsPassConfig::addPreEmitPass() {
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MipsTargetMachine &TM = getMipsTargetMachine();
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addPass(createMipsDelaySlotFillerPass(TM));
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addPass(createMipsLongBranchPass(TM));
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addPass(createMipsConstantIslandPass(TM));
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}
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