a6065f0fa5
This combines the previously posted patches with some additional work I've done to more closely match MSVC output. Most of the important logic here is implemented in AArch64Arm64ECCallLowering. The purpose of the AArch64Arm64ECCallLowering is to take "normal" IR we'd generate for other targets, and generate most of the Arm64EC-specific bits: generating thunks, mangling symbols, generating aliases, and generating the .hybmp$x table. This is all done late for a few reasons: to consolidate the logic as much as possible, and to ensure the IR exposed to optimization passes doesn't contain complex arm64ec-specific constructs. The other changes are supporting changes, to handle the new constructs generated by that pass. There's a global llvm.arm64ec.symbolmap representing the .hybmp$x entries for the thunks. This gets handled directly by the AsmPrinter because it needs symbol indexes that aren't available before that. There are two new calling conventions used to represent calls to and from thunks: ARM64EC_Thunk_X64 and ARM64EC_Thunk_Native. There are a few changes to handle the associated exception-handling info, SEH_SaveAnyRegQP and SEH_SaveAnyRegQPX. I've intentionally left out handling for structs with small non-power-of-two sizes, because that's easily separated out. The rest of my current work is here. I squashed my current patches because they were split in ways that didn't really make sense. Maybe I could split out some bits, but it's hard to meaningfully test most of the parts independently. Thanks to @dpaoliello for extensive testing and suggestions. (Originally posted as https://reviews.llvm.org/D157547 .)
543 lines
18 KiB
C++
543 lines
18 KiB
C++
//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AArch64 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64Subtarget.h"
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#include "AArch64.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64PBQPRegAlloc.h"
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#include "AArch64TargetMachine.h"
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#include "GISel/AArch64CallLowering.h"
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#include "GISel/AArch64LegalizerInfo.h"
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#include "GISel/AArch64RegisterBankInfo.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/TargetParser/AArch64TargetParser.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-subtarget"
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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#include "AArch64GenSubtargetInfo.inc"
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static cl::opt<bool>
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EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
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"converter pass"), cl::init(true), cl::Hidden);
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// If OS supports TBI, use this flag to enable it.
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static cl::opt<bool>
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UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
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"an address is ignored"), cl::init(false), cl::Hidden);
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static cl::opt<bool>
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UseNonLazyBind("aarch64-enable-nonlazybind",
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cl::desc("Call nonlazybind functions via direct GOT load"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
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cl::desc("Enable the use of AA during codegen."));
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static cl::opt<unsigned> OverrideVectorInsertExtractBaseCost(
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"aarch64-insert-extract-base-cost",
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cl::desc("Base cost of vector insert/extract element"), cl::Hidden);
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// Reserve a list of X# registers, so they are unavailable for register
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// allocator, but can still be used as ABI requests, such as passing arguments
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// to function call.
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static cl::list<std::string>
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ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical "
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"registers, so they can't be used by register allocator. "
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"Should only be used for testing register allocator."),
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cl::CommaSeparated, cl::Hidden);
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static cl::opt<bool> ForceStreamingCompatibleSVE(
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"force-streaming-compatible-sve",
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cl::desc(
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"Force the use of streaming-compatible SVE code for all functions"),
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cl::Hidden);
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static cl::opt<AArch64PAuth::AuthCheckMethod>
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AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method",
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cl::Hidden,
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cl::desc("Override the variant of check applied "
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"to authenticated LR during tail call"),
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cl::values(AUTH_CHECK_METHOD_CL_VALUES_LR));
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static cl::opt<unsigned> AArch64MinimumJumpTableEntries(
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"aarch64-min-jump-table-entries", cl::init(13), cl::Hidden,
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cl::desc("Set minimum number of entries to use a jump table on AArch64"));
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unsigned AArch64Subtarget::getVectorInsertExtractBaseCost() const {
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if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)
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return OverrideVectorInsertExtractBaseCost;
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return VectorInsertExtractBaseCost;
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}
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AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(
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StringRef FS, StringRef CPUString, StringRef TuneCPUString,
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bool HasMinSize) {
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// Determine default and user-specified characteristics
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if (CPUString.empty())
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CPUString = "generic";
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if (TuneCPUString.empty())
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TuneCPUString = CPUString;
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ParseSubtargetFeatures(CPUString, TuneCPUString, FS);
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initializeProperties(HasMinSize);
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return *this;
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}
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void AArch64Subtarget::initializeProperties(bool HasMinSize) {
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// Initialize CPU specific properties. We should add a tablegen feature for
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// this in the future so we can specify it together with the subtarget
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// features.
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switch (ARMProcFamily) {
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case Others:
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break;
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case Carmel:
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CacheLineSize = 64;
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break;
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case CortexA35:
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case CortexA53:
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case CortexA55:
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(16);
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MaxBytesForLoopAlignment = 8;
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break;
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case CortexA57:
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MaxInterleaveFactor = 4;
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(16);
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MaxBytesForLoopAlignment = 8;
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break;
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case CortexA65:
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PrefFunctionAlignment = Align(8);
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break;
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case CortexA72:
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case CortexA73:
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case CortexA75:
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(16);
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MaxBytesForLoopAlignment = 8;
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break;
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case CortexA76:
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case CortexA77:
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case CortexA78:
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case CortexA78C:
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case CortexR82:
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case CortexX1:
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case CortexX1C:
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(32);
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MaxBytesForLoopAlignment = 16;
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break;
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case CortexA510:
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case CortexA520:
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PrefFunctionAlignment = Align(16);
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VScaleForTuning = 1;
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PrefLoopAlignment = Align(16);
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MaxBytesForLoopAlignment = 8;
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break;
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case CortexA710:
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case CortexA715:
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case CortexA720:
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case CortexX2:
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case CortexX3:
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case CortexX4:
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PrefFunctionAlignment = Align(16);
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VScaleForTuning = 1;
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PrefLoopAlignment = Align(32);
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MaxBytesForLoopAlignment = 16;
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break;
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case A64FX:
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CacheLineSize = 256;
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PrefFunctionAlignment = Align(8);
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PrefLoopAlignment = Align(4);
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MaxInterleaveFactor = 4;
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PrefetchDistance = 128;
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MinPrefetchStride = 1024;
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MaxPrefetchIterationsAhead = 4;
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VScaleForTuning = 4;
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break;
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case AppleA7:
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case AppleA10:
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case AppleA11:
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case AppleA12:
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case AppleA13:
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case AppleA14:
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case AppleA15:
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case AppleA16:
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case AppleA17:
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CacheLineSize = 64;
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PrefetchDistance = 280;
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MinPrefetchStride = 2048;
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MaxPrefetchIterationsAhead = 3;
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switch (ARMProcFamily) {
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case AppleA14:
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case AppleA15:
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case AppleA16:
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case AppleA17:
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MaxInterleaveFactor = 4;
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break;
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default:
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break;
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}
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break;
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case ExynosM3:
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MaxInterleaveFactor = 4;
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MaxJumpTableSize = 20;
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PrefFunctionAlignment = Align(32);
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PrefLoopAlignment = Align(16);
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break;
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case Falkor:
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MaxInterleaveFactor = 4;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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CacheLineSize = 128;
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PrefetchDistance = 820;
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MinPrefetchStride = 2048;
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MaxPrefetchIterationsAhead = 8;
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break;
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case Kryo:
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MaxInterleaveFactor = 4;
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VectorInsertExtractBaseCost = 2;
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CacheLineSize = 128;
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PrefetchDistance = 740;
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MinPrefetchStride = 1024;
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MaxPrefetchIterationsAhead = 11;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case NeoverseE1:
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PrefFunctionAlignment = Align(8);
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break;
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case NeoverseN1:
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(32);
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MaxBytesForLoopAlignment = 16;
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break;
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case NeoverseN2:
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case NeoverseV2:
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(32);
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MaxBytesForLoopAlignment = 16;
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VScaleForTuning = 1;
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break;
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case NeoverseV1:
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(32);
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MaxBytesForLoopAlignment = 16;
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VScaleForTuning = 2;
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DefaultSVETFOpts = TailFoldingOpts::Simple;
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break;
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case Neoverse512TVB:
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PrefFunctionAlignment = Align(16);
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VScaleForTuning = 1;
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MaxInterleaveFactor = 4;
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break;
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case Saphira:
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MaxInterleaveFactor = 4;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case ThunderX2T99:
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CacheLineSize = 64;
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PrefFunctionAlignment = Align(8);
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PrefLoopAlignment = Align(4);
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MaxInterleaveFactor = 4;
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PrefetchDistance = 128;
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MinPrefetchStride = 1024;
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MaxPrefetchIterationsAhead = 4;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case ThunderX:
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case ThunderXT88:
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case ThunderXT81:
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case ThunderXT83:
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CacheLineSize = 128;
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PrefFunctionAlignment = Align(8);
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PrefLoopAlignment = Align(4);
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case TSV110:
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CacheLineSize = 64;
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(4);
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break;
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case ThunderX3T110:
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CacheLineSize = 64;
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(4);
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MaxInterleaveFactor = 4;
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PrefetchDistance = 128;
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MinPrefetchStride = 1024;
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MaxPrefetchIterationsAhead = 4;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case Ampere1:
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case Ampere1A:
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CacheLineSize = 64;
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PrefFunctionAlignment = Align(64);
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PrefLoopAlignment = Align(64);
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MaxInterleaveFactor = 4;
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break;
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}
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if (AArch64MinimumJumpTableEntries.getNumOccurrences() > 0 || !HasMinSize)
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MinimumJumpTableEntries = AArch64MinimumJumpTableEntries;
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}
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AArch64Subtarget::AArch64Subtarget(const Triple &TT, StringRef CPU,
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StringRef TuneCPU, StringRef FS,
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const TargetMachine &TM, bool LittleEndian,
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unsigned MinSVEVectorSizeInBitsOverride,
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unsigned MaxSVEVectorSizeInBitsOverride,
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bool StreamingSVEMode,
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bool StreamingCompatibleSVEMode,
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bool HasMinSize)
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: AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),
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ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
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ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()),
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CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
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IsLittle(LittleEndian), StreamingSVEMode(StreamingSVEMode),
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StreamingCompatibleSVEMode(StreamingCompatibleSVEMode),
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MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
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MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
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InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU, HasMinSize)),
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TLInfo(TM, *this) {
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if (AArch64::isX18ReservedByDefault(TT))
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ReserveXRegister.set(18);
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CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
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InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));
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Legalizer.reset(new AArch64LegalizerInfo(*this));
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auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
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// FIXME: At this point, we can't rely on Subtarget having RBI.
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// It's awkward to mix passing RBI and the Subtarget; should we pass
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// TII/TRI as well?
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InstSelector.reset(createAArch64InstructionSelector(
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*static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
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RegBankInfo.reset(RBI);
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auto TRI = getRegisterInfo();
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StringSet<> ReservedRegNames;
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ReservedRegNames.insert(ReservedRegsForRA.begin(), ReservedRegsForRA.end());
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for (unsigned i = 0; i < 29; ++i) {
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if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i)))
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ReserveXRegisterForRA.set(i);
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}
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// X30 is named LR, so we can't use TRI->getName to check X30.
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if (ReservedRegNames.count("X30") || ReservedRegNames.count("LR"))
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ReserveXRegisterForRA.set(30);
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// X29 is named FP, so we can't use TRI->getName to check X29.
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if (ReservedRegNames.count("X29") || ReservedRegNames.count("FP"))
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ReserveXRegisterForRA.set(29);
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AddressCheckPSV.reset(new AddressCheckPseudoSourceValue(TM));
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}
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const CallLowering *AArch64Subtarget::getCallLowering() const {
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return CallLoweringInfo.get();
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}
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const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const {
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return InlineAsmLoweringInfo.get();
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}
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InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
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return InstSelector.get();
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}
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const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
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return Legalizer.get();
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}
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const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
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return RegBankInfo.get();
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}
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/// Find the target operand flags that describe how a global value should be
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/// referenced for the current subtarget.
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unsigned
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AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
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const TargetMachine &TM) const {
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// MachO large model always goes via a GOT, simply to get a single 8-byte
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// absolute relocation on all global addresses.
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if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
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return AArch64II::MO_GOT;
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// All globals dynamically protected by MTE must have their address tags
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// synthesized. This is done by having the loader stash the tag in the GOT
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// entry. Force all tagged globals (even ones with internal linkage) through
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// the GOT.
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if (GV->isTagged())
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return AArch64II::MO_GOT;
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if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
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if (GV->hasDLLImportStorageClass()) {
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return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
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}
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if (getTargetTriple().isOSWindows())
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return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
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return AArch64II::MO_GOT;
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}
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// The small code model's direct accesses use ADRP, which cannot
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// necessarily produce the value 0 (if the code is above 4GB).
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// Same for the tiny code model, where we have a pc relative LDR.
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if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
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GV->hasExternalWeakLinkage())
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return AArch64II::MO_GOT;
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// References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
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// that their nominal addresses are tagged and outside of the code model. In
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// AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
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// tag if necessary based on MO_TAGGED.
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if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
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return AArch64II::MO_NC | AArch64II::MO_TAGGED;
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return AArch64II::MO_NO_FLAG;
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}
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unsigned AArch64Subtarget::classifyGlobalFunctionReference(
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const GlobalValue *GV, const TargetMachine &TM) const {
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// MachO large model always goes via a GOT, because we don't have the
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// relocations available to do anything else..
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if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
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!GV->hasInternalLinkage())
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return AArch64II::MO_GOT;
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// NonLazyBind goes via GOT unless we know it's available locally.
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auto *F = dyn_cast<Function>(GV);
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if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
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!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
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return AArch64II::MO_GOT;
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if (getTargetTriple().isOSWindows()) {
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if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy()) {
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if (GV->hasDLLImportStorageClass()) {
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// On Arm64EC, if we're calling a symbol from the import table
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// directly, use MO_ARM64EC_CALLMANGLE.
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return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT |
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AArch64II::MO_ARM64EC_CALLMANGLE;
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}
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if (GV->hasExternalLinkage()) {
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// If we're calling a symbol directly, use the mangled form in the
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// call instruction.
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return AArch64II::MO_ARM64EC_CALLMANGLE;
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}
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}
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// Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
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return ClassifyGlobalReference(GV, TM);
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}
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return AArch64II::MO_NO_FLAG;
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}
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void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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unsigned NumRegionInstrs) const {
|
|
// LNT run (at least on Cyclone) showed reasonably significant gains for
|
|
// bi-directional scheduling. 253.perlbmk.
|
|
Policy.OnlyTopDown = false;
|
|
Policy.OnlyBottomUp = false;
|
|
// Enabling or Disabling the latency heuristic is a close call: It seems to
|
|
// help nearly no benchmark on out-of-order architectures, on the other hand
|
|
// it regresses register pressure on a few benchmarking.
|
|
Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
|
|
}
|
|
|
|
bool AArch64Subtarget::enableEarlyIfConversion() const {
|
|
return EnableEarlyIfConvert;
|
|
}
|
|
|
|
bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
|
|
if (!UseAddressTopByteIgnored)
|
|
return false;
|
|
|
|
if (TargetTriple.isDriverKit())
|
|
return true;
|
|
if (TargetTriple.isiOS()) {
|
|
return TargetTriple.getiOSVersion() >= VersionTuple(8);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
std::unique_ptr<PBQPRAConstraint>
|
|
AArch64Subtarget::getCustomPBQPConstraints() const {
|
|
return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
|
|
}
|
|
|
|
void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
|
|
// We usually compute max call frame size after ISel. Do the computation now
|
|
// if the .mir file didn't specify it. Note that this will probably give you
|
|
// bogus values after PEI has eliminated the callframe setup/destroy pseudo
|
|
// instructions, specify explicitly if you need it to be correct.
|
|
MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
if (!MFI.isMaxCallFrameSizeComputed())
|
|
MFI.computeMaxCallFrameSize(MF);
|
|
}
|
|
|
|
bool AArch64Subtarget::useAA() const { return UseAA; }
|
|
|
|
bool AArch64Subtarget::isStreamingCompatible() const {
|
|
return StreamingCompatibleSVEMode || ForceStreamingCompatibleSVE;
|
|
}
|
|
|
|
bool AArch64Subtarget::isNeonAvailable() const {
|
|
return hasNEON() &&
|
|
(hasSMEFA64() || (!isStreaming() && !isStreamingCompatible()));
|
|
}
|
|
|
|
bool AArch64Subtarget::isSVEAvailable() const {
|
|
return hasSVE() &&
|
|
(hasSMEFA64() || (!isStreaming() && !isStreamingCompatible()));
|
|
}
|
|
|
|
// If return address signing is enabled, tail calls are emitted as follows:
|
|
//
|
|
// ```
|
|
// <authenticate LR>
|
|
// <check LR>
|
|
// TCRETURN ; the callee may sign and spill the LR in its prologue
|
|
// ```
|
|
//
|
|
// LR may require explicit checking because if FEAT_FPAC is not implemented
|
|
// and LR was tampered with, then `<authenticate LR>` will not generate an
|
|
// exception on its own. Later, if the callee spills the signed LR value and
|
|
// neither FEAT_PAuth2 nor FEAT_EPAC are implemented, the valid PAC replaces
|
|
// the higher bits of LR thus hiding the authentication failure.
|
|
AArch64PAuth::AuthCheckMethod
|
|
AArch64Subtarget::getAuthenticatedLRCheckMethod() const {
|
|
if (AuthenticatedLRCheckMethod.getNumOccurrences())
|
|
return AuthenticatedLRCheckMethod;
|
|
|
|
// At now, use None by default because checks may introduce an unexpected
|
|
// performance regression or incompatibility with execute-only mappings.
|
|
return AArch64PAuth::AuthCheckMethod::None;
|
|
}
|