Michael Maitland 3967510032 [RISCV][GISel] First mask argument placed in v0 according to RISCV Ve… (#79343) ...

…ctor CC.

2024-01-24 16:03:38 -05:00

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AArch64

[AArch64] Add vec3 tests with different load/store alignments.

2024-01-24 14:19:33 +00:00

AMDGPU

[AMDGPU] Move architected SGPR implementation into isel (#79120)

2024-01-24 15:06:20 +00:00

ARC

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ARM

[Thumb,ELF] Fix access to dso_preemptable __stack_chk_guard with static relocation model (#78950)

2024-01-22 13:16:31 -08:00

AVR

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BPF

[InstCombine] Canonicalize constant GEPs to i8 source element type (#68882)

2024-01-24 15:25:29 +01:00

CSKY

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DirectX

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Generic

[AsmPrinter] Remove mbb-profile-dump flag (#76595)

2024-01-23 16:48:10 -08:00

Hexagon

[HEXAGON] Inlining Division (#79021)

2024-01-24 09:30:33 -06:00

Inputs

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Lanai

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LoongArch

[CodeGen][LoongArch] Set FP_TO_SINT/FP_TO_UINT to legal for vector types (#79107)

2024-01-23 15:57:06 +08:00

M68k

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Mips

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MIR

[AMDGPU] Add mark last scratch load pass (#75512)

2024-01-18 09:36:44 +01:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] use incomplete aggregate initializers (#79062)

2024-01-24 09:24:28 -08:00

PowerPC

Require asserts for llvm/test/CodeGen/PowerPC/sms-regpress.mir.

2024-01-22 13:51:03 -08:00

RISCV

[RISCV][GISel] First mask argument placed in v0 according to RISCV Ve… (#79343)

2024-01-24 16:03:38 -05:00

SPARC

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SPIRV

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SystemZ

[SystemZ] Require D12 for i128 accesses in isLegalAddressingMode() (#79221)

2024-01-24 20:16:05 +01:00

Thumb

[test] Update stack_guard_remat.ll (#79139)

2024-01-23 14:48:33 +01:00

Thumb2

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VE

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WebAssembly

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WinCFGuard

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WinEH

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X86

[DebugNames] Implement Entry::GetParentEntry query (#78760)

2024-01-24 06:44:03 -08:00

XCore

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