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clang-p2996/llvm/lib/Target/RISCV
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Craig Topper 04107797d9 [RISCV][GISel] Simplify some code. NFC 
typeIs and LegalizeMutation::changeTo instead of implementing our own lambdas
that do the same thing.
2023-11-13 15:27:41 -08:00
..
AsmParser
[llvm] Stop including llvm/ADT/SmallString.h (NFC)
2023-11-11 12:32:13 -08:00
Disassembler
[RISCV] Support Xsfvfnrclipxfqf extensions (#68297)
2023-11-03 10:52:37 +08:00
GISel
[RISCV][GISel] Simplify some code. NFC
2023-11-13 15:27:41 -08:00
MCA
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
MCTargetDesc
[RISCV] Support R_RISCV_SET_ULEB128/R_RISCV_SUB_ULEB128 for .uleb128 directives
2023-11-09 09:27:32 -08:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add missing component Scalar (#71905)
2023-11-10 16:43:42 +08:00
RISCV.h
[RISCV] Implement cross basic block VXRM write insertion. (#70382)
2023-11-02 14:09:27 -07:00
RISCV.td
…
RISCVAsmPrinter.cpp
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
[RISCV][CodeGenPrepare] Remove duplicated transform for zext. NFC. (#72053)
2023-11-13 22:45:33 +08:00
RISCVCombine.td
…
RISCVDeadRegisterDefinitions.cpp
…
RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
…
RISCVFeatures.td
[RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (#71140)
2023-11-06 11:22:14 +08:00
RISCVFoldMasks.cpp
[RISCV] Begin moving post-isel vector peepholes to a MF pass (#70342)
2023-10-30 15:17:00 +00:00
RISCVFrameLowering.cpp
[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)
2023-09-25 12:05:05 +08:00
RISCVFrameLowering.h
…
RISCVGatherScatterLowering.cpp
…
RISCVGISel.td
[RISCV] Add an slli.uw pattern using zext for -riscv-experimental-rv64-legal-i32
2023-11-11 14:41:56 -08:00
RISCVInsertReadWriteCSR.cpp
[RISCV] Implement cross basic block VXRM write insertion. (#70382)
2023-11-02 14:09:27 -07:00
RISCVInsertVSETVLI.cpp
[RISCVInsertVSETVLI] Allow PRE with non-immediate AVLs (#71728)
2023-11-09 08:03:13 -08:00
RISCVInsertWriteVXRM.cpp
[RISCV] Implement cross basic block VXRM write insertion. (#70382)
2023-11-02 14:09:27 -07:00
RISCVInstrFormats.td
…
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrInfo.cpp
[RISCV][GISel] Select G_BRCOND and G_ICMP together when possible.
2023-11-12 15:53:23 -08:00
RISCVInstrInfo.h
[RISCV][GISel] Select G_BRCOND and G_ICMP together when possible.
2023-11-12 15:53:23 -08:00
RISCVInstrInfo.td
[RISCV] Select zext as sext when sign bit is 0 for -riscv-experimental-rv64-legal-i32
2023-11-13 12:21:36 -08:00
RISCVInstrInfoA.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoC.td
[RISCV] Add CompressPat for c.beqz/bnez with X0 in the first operand. (#69042)
2023-10-14 08:12:46 -07:00
RISCVInstrInfoD.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoF.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoM.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Use masked pseudo peephole for reduction pseudos (#71508)
2023-11-08 12:46:06 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Use masked pseudo peephole for reduction pseudos (#71508)
2023-11-08 12:46:06 +08:00
RISCVInstrInfoXCV.td
…
RISCVInstrInfoXSf.td
[RISCV] Support Xsfvfnrclipxfqf extensions (#68297)
2023-11-03 10:52:37 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoZb.td
[RISCV] Add more packh patterns.
2023-11-11 19:31:23 -08:00
RISCVInstrInfoZc.td
[RISCV][NFC] Correct RISCVInstrInfoZc.td header comment - Zc* extensions no longer experimental
2023-10-10 16:41:27 +01:00
RISCVInstrInfoZfa.td
[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633)
2023-10-19 14:55:33 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoZicbo.td
[RISCV] Match prefetch address with offset (#66072)
2023-10-20 14:22:48 +08:00
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZk.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoZvfbf.td
…
RISCVInstrInfoZvk.td
[RISCV] Fix wrong implication for zvknhb. (#66860)
2023-11-03 09:32:21 +08:00
RISCVISelDAGToDAG.cpp
[RISCV] Fix lowering of negative zero with Zdinx 32-bit (#71869)
2023-11-13 07:38:14 +01:00
RISCVISelDAGToDAG.h
[RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. (#71483)
2023-11-07 16:21:35 +08:00
RISCVISelLowering.cpp
[RISCV][SDAG] Prefer ShortForwardBranch to lower sdiv by pow2 (#67364)
2023-11-10 21:38:47 +08:00
RISCVISelLowering.h
[RISCV][SDAG] Prefer ShortForwardBranch to lower sdiv by pow2 (#67364)
2023-11-10 21:38:47 +08:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)
2023-09-25 12:05:05 +08:00
RISCVMacroFusion.cpp
[RISCV] Remove FrameIndex case in lui+addi MacroFusion (#68701)
2023-10-19 13:32:44 +08:00
RISCVMacroFusion.h
…
RISCVMakeCompressible.cpp
[RegScavenger] Simplify state tracking for backwards scavenging (#71202)
2023-11-08 09:49:07 +00:00
RISCVMergeBaseOffset.cpp
…
RISCVMoveMerger.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-10-21 10:52:24 -07:00
RISCVOptWInstrs.cpp
[RISCV] Teach RISCVOptWInstrs that 'bset x0, 30-0' satisfies isSignExtendingOpW.
2023-11-01 12:29:37 -07:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)
2023-11-09 15:15:23 +08:00
RISCVProcessors.td
[RISCV] Enable LoopDataPrefetch pass (#66201)
2023-11-10 15:39:58 +08:00
RISCVPushPopOptimizer.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-10-21 10:52:24 -07:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV][NFC] Use !range bang operator (#66494)
2023-10-20 12:06:01 +08:00
RISCVRVVInitUndef.cpp
[RISCV] Add sink-and-fold support for RISC-V. (#67602)
2023-10-07 10:38:35 -07:00
RISCVSchedRocket.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVSchedSiFive7.td
[RISCV] SiFive7 VLDS Sched should not depend on VL when stride is x0. (#70266)
2023-10-30 15:47:45 -04:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVSchedule.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVScheduleV.td
[RISCV] SiFive7 VLDS Sched should not depend on VL when stride is x0. (#70266)
2023-10-30 15:47:45 -04:00
RISCVScheduleZb.td
…
RISCVSubtarget.cpp
[RISCV] Add searchable table for tune information (#66193)
2023-09-26 12:26:35 +08:00
RISCVSubtarget.h
[RISCV] Enable LoopDataPrefetch pass (#66201)
2023-11-10 15:39:58 +08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV] Enable LoopDataPrefetch pass (#66201)
2023-11-10 15:39:58 +08:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)
2023-11-09 15:15:23 +08:00
RISCVTargetTransformInfo.h
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
2023-09-25 12:26:01 +03:00