db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
34 lines
1.2 KiB
LLVM
34 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-eabi | FileCheck %s
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; DAG ends up with two uses for the flags from an ADCS node, which means they
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; must be saved for later.
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define void @f(ptr nocapture %a, ptr nocapture %b, ptr nocapture %cc, ptr nocapture %dd) nounwind uwtable noinline ssp {
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; CHECK-LABEL: f:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldp x8, x10, [x2]
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; CHECK-NEXT: ldp x9, x11, [x3]
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; CHECK-NEXT: ldp x13, x12, [x2, #16]
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; CHECK-NEXT: adds x8, x8, x9
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; CHECK-NEXT: ldp x14, x9, [x3, #16]
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; CHECK-NEXT: adcs x10, x10, x11
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; CHECK-NEXT: stp x8, x10, [x0]
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; CHECK-NEXT: adcs x11, x13, x14
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; CHECK-NEXT: adc x13, x12, x9
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; CHECK-NEXT: orr x12, x12, #0x100
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; CHECK-NEXT: adc x9, x12, x9
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; CHECK-NEXT: stp x11, x13, [x0, #16]
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; CHECK-NEXT: stp x11, x9, [x1, #16]
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; CHECK-NEXT: stp x8, x10, [x1]
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; CHECK-NEXT: ret
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entry:
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%c = load i256, ptr %cc
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%d = load i256, ptr %dd
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%add = add nsw i256 %c, %d
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store i256 %add, ptr %a, align 8
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%or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376
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%add6 = add nsw i256 %or, %d
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store i256 %add6, ptr %b, align 8
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ret void
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}
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