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clang-p2996/llvm/test/CodeGen/RISCV/rvv
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Philip Reames 7ac8486e54 [RISCVInsertVSETVLI] Allow PRE with non-immediate AVLs (#71728) 
Extend our PRE logic to cover non-immediate AVL values. This covers
large constant AVLs (which must be materialized in registers), and may
help some code written explicitly with intrinsics.

Looking at the existing code, I can't entirely figure out why I thought
we needed VL == AVL to perform the PRE. My best guess is that I was
worried about the VLMAX < VL < 2 * VLMAX case, but the spec explicitly
says that vsetvli must be determinist on any particular AVL value.

That case was, possibly by accident, covering another legality
precondition. Specifically, by only returning true for immediate and
VLMAX AVL values, we didn't encounter the case where the AVL was a
register and that register wasn't available in the predecessor (e.g. if
AVL is a load in the MBB block itself).

---------

Co-authored-by: Luke Lau <luke_lau@icloud.com>
2023-11-09 08:03:13 -08:00
..
abs-sdnode.ll
…
abs-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
access-fixed-objects-by-rvv.ll
…
active_lane_mask.ll
[RISCV] Be more aggressive about shrinking constant build_vector etype (#67175)
2023-09-25 08:09:46 -07:00
addi-rvv-stack-object.mir
…
addi-scalable-offset.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
aliases.mir
…
alloca-load-store-scalable-array.ll
[IR] Enable load/store/alloca for arrays of scalable vectors.
2023-09-14 13:49:01 +00:00
alloca-load-store-scalable-struct.ll
[SelectionDAG] Use TypeSize variant of ComputeValueVTs to compute correct offsets for scalable aggregate types.
2023-08-16 11:56:31 +00:00
allocate-lmul-2-4-8.ll
…
allone-masked-to-unmasked.ll
…
binop-splats.ll
[RISCV] Add tests where bin ops of splats could be scalarized. NFC (#65747)
2023-09-20 13:23:56 +01:00
bitreverse-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
bitreverse-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
bswap-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
bswap-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
calling-conv-fastcc.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
calling-conv.ll
…
ceil-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
cmp-folds.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
combine-sats.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
combine-splats.ll
[RISCV] Fix test using wrong variable. NFC
2023-08-24 15:45:43 +01:00
combine-store.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
combine-vmv.ll
[RISCV] Fold ops into vmv.v.v as vmerge with all-ones mask
2023-07-19 17:24:42 +01:00
common-shuffle-patterns.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
commuted-op-indices-regression.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
concat-vectors-constant-stride.ll
[RISCV] Improve performCONCAT_VECTORCombine stride matching
2023-10-16 16:45:26 -07:00
constant-folding-crash.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
constant-folding.ll
[RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419)
2023-09-27 19:53:50 +01:00
copyprop.mir
[RISCV] Add isMoveReg to vmv1r/vmv2r/vmv4r/vmv8r.v.
2023-07-18 09:49:23 -07:00
cross-block-cse.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
ctlz-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
ctlz-vp.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
ctpop-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
ctpop-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
cttz-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
cttz-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
debug-info-rvv-dbg-value.mir
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
double-round-conv.ll
[RISCV] Stop performFP_TO_INTCombine from folding with ISD::FRINT.
2023-08-10 09:30:36 -07:00
emergency-slot.mir
[RISCV] Don't set KILL flag on X0 in RISCVInstrInfo::movImm.
2023-09-25 13:40:08 -07:00
expand-no-v.ll
…
extload-truncstore.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
extract-subvector.ll
[DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types
2023-08-18 12:28:27 -07:00
extractelt-fp.ll
[RISCV] Reduce LMUL for vector extracts
2023-08-22 07:36:17 -07:00
extractelt-i1.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
extractelt-int-rv32.ll
[RISCV] Reduce LMUL for vector extracts
2023-08-22 07:36:17 -07:00
extractelt-int-rv64.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fceil-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fceil-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
ffloor-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
ffloor-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-abs-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-abs.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-binop-splats.ll
[RISCV] Add tests where bin ops of splats could be scalarized. NFC (#65747)
2023-09-20 13:23:56 +01:00
fixed-vectors-bitcast-large-vector.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-bitcast.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-bitreverse-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-bitreverse.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-bswap-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-bswap.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-buildvec-of-binop.ll
[RISCV] Fix assertion failure from performBUILD_VECTORCombine when the binop is a shift. (#69349)
2023-10-18 21:40:28 -07:00
fixed-vectors-calling-conv-fastcc.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-calling-conv.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-ceil-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-ctlz-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-ctlz.ll
[RISCV] Add _RM pseudos to pseudos table (#70693)
2023-10-31 08:41:56 +00:00
fixed-vectors-ctpop-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-ctpop.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-cttz-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-cttz.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-deinterleave-load.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-elen.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-emergency-slot.mir
…
fixed-vectors-extload-truncstore.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-extract-i1.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-extract-subvector.ll
[RISCV] Shrink vslidedown when lowering fixed extract_subvector (#65598)
2023-09-11 17:25:12 +01:00
fixed-vectors-extract.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-fceil-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-ffloor-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-floor-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-fmaximum.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-fmf.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fminimum.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-fnearbyint-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-fp2i-sat.ll
[RISCV] Lower fixed vectors extract_vector_elt through stack at high LMUL
2023-09-11 10:49:17 -07:00
fixed-vectors-fp2i.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
fixed-vectors-fp-bitcast.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fp-buildvec.ll
[RISCV] Fix illegal build_vector when lowering double id buildvec on RV32 (#67017)
2023-10-04 21:28:44 +01:00
fixed-vectors-fp-conv.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fp-interleave.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-fp-setcc.ll
[RISCV] Promote SETCC and VP_SETCC of f16 vectors when only have zvfhmin (#66866)
2023-09-27 11:00:19 +08:00
fixed-vectors-fp-shuffles.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-fp-splat.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fp-vrgather.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fpext-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fptosi-vp-mask.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
fixed-vectors-fptosi-vp.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
fixed-vectors-fptoui-vp-mask.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
fixed-vectors-fptoui-vp.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
fixed-vectors-fptrunc-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fround-costrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-fround.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-froundeven-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-froundeven.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-fshr-fshl-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-ftrunc-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-i2fp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-insert-i1.ll
[RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)
2023-09-27 20:26:36 +01:00
fixed-vectors-insert-subvector-shuffle.ll
[RISCV] Fold ops into vmv.v.v as vmerge with all-ones mask
2023-07-19 17:24:42 +01:00
fixed-vectors-insert-subvector.ll
Revert "[RISCV] Shrink vslideup's LMUL when lowering fixed insert_subvector (#65997)"
2023-10-10 15:13:57 -07:00
fixed-vectors-insert.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-int-buildvec.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-int-explodevector.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-int-exttrunc.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-int-interleave.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-int-setcc.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-int-shuffles.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-int-splat.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-int-vrgather.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-int.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-interleave-store.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
fixed-vectors-interleaved-access-zve32x.ll
[RISCV] Form vmv.s.f/x from single element splats via DAG combine
2023-08-30 12:44:36 -07:00
fixed-vectors-interleaved-access.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-inttoptr-ptrtoint.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-llrint.ll
LegalizeVectorTypes: fix bug in widening of vec result in xrint (#71198)
2023-11-03 21:04:09 +00:00
fixed-vectors-load-store.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-load.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-lrint.ll
LegalizeVectorTypes: fix bug in widening of vec result in xrint (#71198)
2023-11-03 21:04:09 +00:00
fixed-vectors-marith-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-mask-buildvec.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-mask-load-store.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-mask-logic.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-mask-splat.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-masked-gather.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-masked-load-fp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-masked-load-int.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-masked-scatter.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-masked-store-fp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-masked-store-int.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-nearbyint-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-peephole-vmerge-vops.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-reduction-formation.ll
[RISCV] Allow swapped operands in reduction formation (#68634)
2023-10-23 10:37:56 -07:00
fixed-vectors-reduction-fp-vp.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-reduction-fp.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-reduction-int-vp.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-reduction-int.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-reduction-mask-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-rint-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-round-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-roundeven-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-roundtozero-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-segN-load.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-segN-store.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
fixed-vectors-select-fp.ll
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
fixed-vectors-select-int.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-setcc-fp-vp.ll
[RISCV] Add FileCheck prefixes for test where RV32/RV64 output differs. NFC
2023-11-06 19:32:07 +08:00
fixed-vectors-setcc-int-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-setcc-int-vp.ll
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
fixed-vectors-sext-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-sext-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-shuffle-extract-subvector.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-shuffle-reverse-bitrotate.ll
[RISCV] Fix crash during during i1 vector bitreverse lowering
2023-08-31 19:39:08 +01:00
fixed-vectors-shuffle-reverse.ll
[RISCV] Be more aggressive about shrinking constant build_vector etype (#67175)
2023-09-25 08:09:46 -07:00
fixed-vectors-shuffle-rotate.ll
[RISCV] Relax some Zvbb patterns and lowerings to Zvkb (#68115)
2023-10-03 17:42:40 +01:00
fixed-vectors-shuffle-transpose.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
fixed-vectors-shuffle-vslide1down.ll
[DAGCombiner] Don't reduce BUILD_VECTOR to BITCAST before LegalizeTypes if VT is legal.
2023-08-19 12:53:50 +08:00
fixed-vectors-shuffle-vslide1up.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-shufflevector-vnsrl.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-sitofp-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-sitofp-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-stepvector.ll
[RISCV] Be more aggressive about shrinking constant build_vector etype (#67175)
2023-09-25 08:09:46 -07:00
fixed-vectors-store-merge-crash.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-store.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fixed-vectors-strided-load-combine.ll
Revert "[RISCV] Shrink vslideup's LMUL when lowering fixed insert_subvector (#65997)"
2023-10-10 15:13:57 -07:00
fixed-vectors-strided-load-store-asm.ll
[RISCVInsertVSETVLI] Allow PRE with non-immediate AVLs (#71728)
2023-11-09 08:03:13 -08:00
fixed-vectors-strided-load-store-negative.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-strided-load-store.ll
[RISCV] Add gather test coverage for non-intptr index widths
2023-09-08 08:53:19 -07:00
fixed-vectors-strided-vpload.ll
[DAGCombiner] Combine vp.strided.load with unit stride to vp.load (#66766)
2023-09-19 16:39:28 +01:00
fixed-vectors-strided-vpstore.ll
[DAGCombiner] Combine vp.strided.store with unit stride to vp.store (#66774)
2023-09-19 16:43:50 +01:00
fixed-vectors-trunc-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-trunc-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fixed-vectors-uitofp-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-uitofp-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-unaligned.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vadd-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vadd-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vand-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vcopysign-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vdiv-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vdivu-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfabs-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfadd-constrained-sdnode.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfadd-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfclass-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfclass.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfcmp-constrained-sdnode.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfcmps-constrained-sdnode.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfdiv-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-vfdiv-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfma-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-vfmacc-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-vfmadd-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-vfmax-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfmax.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfmin-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfmin.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfmsac-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-vfmsub-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-vfmul-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-vfmul-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfmuladd-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-vfneg-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfnmacc-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-vfnmadd-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-vfnmsac-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-vfnmsub-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-vfpext-constrained-sdnode.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfptoi-constrained-sdnode.ll
[RISCVInsertVSETVLI] Default to VL=1 for scalar extracts
2023-08-16 07:35:00 -07:00
fixed-vectors-vfptrunc-constrained-sdnode.ll
[RISCV] Support STRICT_FP_ROUND and STRICT_FP_EXTEND when only have Zvfhmin (#68559)
2023-10-17 10:10:19 +08:00
fixed-vectors-vfrdiv-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfrsub-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfsqrt-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-vfsqrt-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfsub-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fixed-vectors-vfsub-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfwadd.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfwmacc.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfwmul.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vfwsub.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vitofp-constrained-sdnode.ll
[RISCV] Form vmv.s.f/x from single element splats via DAG combine
2023-08-30 12:44:36 -07:00
fixed-vectors-vmacc-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-vmax-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vmaxu-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vmin-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vminu-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vmul-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vmul-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vnmsac-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fixed-vectors-vnsra-vnsrl.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vor-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vpgather.ll
[RISCV] Move narrowIndex to be a DAG combine over target independent nodes
2023-09-15 15:02:14 -07:00
fixed-vectors-vpload.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vpmerge.ll
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
fixed-vectors-vpscatter.ll
[RISCV] Move narrowIndex to be a DAG combine over target independent nodes
2023-09-15 15:02:14 -07:00
fixed-vectors-vpstore.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vreductions-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vrem-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vremu-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vrol.ll
[RISCV] Relax some Zvbb patterns and lowerings to Zvkb (#68115)
2023-10-03 17:42:40 +01:00
fixed-vectors-vror.ll
[RISCV] Relax some Zvbb patterns and lowerings to Zvkb (#68115)
2023-10-03 17:42:40 +01:00
fixed-vectors-vrsub-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsadd.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsaddu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vscale-range.ll
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
fixed-vectors-vselect-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fixed-vectors-vselect.ll
[RISCV] Transform build_vector((binop X_i, C_i)..) to binop (build_vector, build_vector) (#67358)
2023-09-26 07:53:35 -07:00
fixed-vectors-vshl-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsra-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsrl-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vssub.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vssubu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsub-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vsub-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vw-web-simplification.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwadd.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwaddu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmacc.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmaccsu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmaccu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmaccus.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmul.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmulsu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwmulu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwsub.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vwsubu.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-vxor-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-xsfvcp-x.ll
[RISCV] Support VLS for VCIX (#67289)
2023-10-07 01:29:51 +08:00
fixed-vectors-xsfvcp-xv.ll
[RISCV] Support VLS for VCIX (#67289)
2023-10-07 01:29:51 +08:00
fixed-vectors-xsfvcp-xvv.ll
[RISCV] Support VLS for VCIX (#67289)
2023-10-07 01:29:51 +08:00
fixed-vectors-xsfvcp-xvw.ll
[RISCV] Support VLS for VCIX (#67289)
2023-10-07 01:29:51 +08:00
fixed-vectors-zext-vp-mask.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fixed-vectors-zext-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
float-round-conv.ll
[RISCV] Stop performFP_TO_INTCombine from folding with ISD::FRINT.
2023-08-10 09:30:36 -07:00
floor-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
fmaximum-sdnode.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fminimum-sdnode.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fnearbyint-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fnearbyint-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fold-binary-reduce.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fold-scalar-load-crash.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
fold-vector-cmp.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
fold-vp-fadd-and-vp-fmul.ll
[DAG] getNode() - remove oneuse limit from (zext (trunc (assertzext x))) -> (assertzext x) fold (REAPPLIED)
2023-09-22 11:01:38 +01:00
fold-vp-fsub-and-vp-fmul.ll
[RISCV] Use mask agnostic policy for masked RISCVISD::VFMADD_VL patterns.
2023-05-15 23:16:38 -07:00
fpclamptosat_vec.ll
Revert "[RISCV] Shrink vslideup's LMUL when lowering fixed insert_subvector (#65997)"
2023-10-10 15:13:57 -07:00
fptosi-sat.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
fptoui-sat.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
frameindex-addr.ll
…
frint-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fround-costrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
fround-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
froundeven-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
froundeven-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
fshr-fshl-vp.ll
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
2023-10-24 22:13:17 +01:00
fshr-fshl.ll
…
ftrunc-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
ftrunc-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
get_vector_length.ll
[RISCV] Lower experimental_get_vector_length intrinsic to vsetvli for some cases.
2023-06-05 15:02:11 -07:00
get-vlen-debugloc.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
half-round-conv.ll
[RISCV] Stop performFP_TO_INTCombine from folding with ISD::FRINT.
2023-08-10 09:30:36 -07:00
implicit-def-copy.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
inline-asm.ll
…
insert-subvector.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
insertelt-fp.ll
[RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)
2023-09-27 20:26:36 +01:00
insertelt-i1.ll
[RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)
2023-09-27 20:26:36 +01:00
insertelt-int-rv32.ll
[RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)
2023-09-27 20:26:36 +01:00
insertelt-int-rv64.ll
[RISCV] Reduce LMUL when index is known when lowering insert_vector_elt (#66087)
2023-09-27 20:26:36 +01:00
interleave-crash.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
large-rvv-stack-size.mir
…
legalize-load-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
legalize-scalable-vectortype.ll
…
legalize-store-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
llrint-sdnode.ll
CodeGen/RISCV: increase test coverage of lrint, llrint (#70826)
2023-10-31 19:16:39 +00:00
load-add-store-8.ll
…
load-add-store-16.ll
…
load-add-store-32.ll
…
load-add-store-64.ll
…
load-mask.ll
…
localvar.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
lrint-sdnode.ll
CodeGen/RISCV: increase test coverage of lrint, llrint (#70826)
2023-10-31 19:16:39 +00:00
marith-vp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
mask-exts-truncs-rv32.ll
…
mask-exts-truncs-rv64.ll
…
mask-reg-alloc.mir
[RISCV] Fix using undefined variable %pt2 in mask-reg-alloc.mir testcase (#70764)
2023-11-07 17:05:03 +08:00
masked-load-fp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
masked-load-int.ll
…
masked-store-fp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
masked-store-int.ll
…
masked-tama.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
masked-tamu.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
masked-tuma.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
masked-tumu.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
masked-vslide1down-rv32.ll
…
memcpy-inline.ll
[RISCV] Implement getOptimalMemOpType for memcpy/memset lowering
2023-08-01 12:14:50 -07:00
memory-args.ll
…
memset-inline.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
mgather-sdnode.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
mscatter-combine.ll
[RISCV] Add a combine to form masked.store from unit strided store
2023-09-19 07:45:35 -07:00
mscatter-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
mutate-prior-vsetvli-avl.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
named-vector-shuffle-reverse.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
narrow-shift-extend.ll
[RISCV] Move narrowIndex to be a DAG combine over target independent nodes
2023-09-15 15:02:14 -07:00
nearbyint-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
no-reserved-frame.ll
…
pass-fast-math-flags-sdnode.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
pr52475.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
pr61561.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
pr63459.ll
[RISCV][SelectionDAGBuilder] Fix an implicit scalable TypeSize to fixed size conversion in getUniformBase.
2023-06-26 11:56:17 -07:00
pr63596.ll
[RISCV] Custom lower FP_TO_FP16 and FP16_TO_FP to correct ABI of of libcall
2023-06-30 16:41:49 +01:00
pr64588.ll
[RISCV] Truncate constants to EltSize when combine store of BUILD_VECTOR
2023-08-14 10:55:53 +08:00
reg-alloc-reserve-bp.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
reg-coalescing.mir
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
regalloc-fast-crash.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
rint-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
round-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
roundeven-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
roundtozero-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
rv32-spill-vector-csr.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
rv32-spill-vector.ll
…
rv32-spill-zvlsseg.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
rv64-spill-vector-csr.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
rv64-spill-vector.ll
…
rv64-spill-zvlsseg.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
rvv-args-by-mem.ll
…
rvv-framelayout.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
rvv-out-arguments.ll
[RISCV] Implement getOptimalMemOpType for memcpy/memset lowering
2023-08-01 12:14:50 -07:00
rvv-peephole-vmerge-masked-vops.ll
[RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. (#71483)
2023-11-07 16:21:35 +08:00
rvv-peephole-vmerge-to-vmv.mir
[RISCV] Begin moving post-isel vector peepholes to a MF pass (#70342)
2023-10-30 15:17:00 +00:00
rvv-peephole-vmerge-vops-mir.ll
…
rvv-peephole-vmerge-vops.ll
[RISCV] Use masked pseudo peephole for reduction pseudos (#71508)
2023-11-08 12:46:06 +08:00
rvv-stack-align.mir
…
rvv-vmerge-to-vmv.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
rvv-vscale.i32.ll
…
rvv-vscale.i64.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
saddo-sdnode.ll
…
scalable-vector-struct.ll
[RISCV] Move some vector tests to rvv directory. NFC
2023-04-06 10:28:41 +01:00
scalar-stack-align.ll
…
select-fp.ll
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
select-int.ll
…
select-sra.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
setcc-fp-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
setcc-fp.ll
[RISCV] Promote SETCC and VP_SETCC of f16 vectors when only have zvfhmin (#66866)
2023-09-27 11:00:19 +08:00
setcc-int-vp-mask.ll
…
setcc-int-vp.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
setcc-integer.ll
[RISCV] Prefer vmsle.vi vX, vY, -1 over vslt.vx vX, vY, x0.
2023-04-24 11:45:27 -07:00
sf_vfnrclip_x_f_qf.ll
[RISCV] Support Xsfvfnrclipxfqf extensions (#68297)
2023-11-03 10:52:37 +08:00
sf_vfnrclip_xu_f_qf.ll
[RISCV] Support Xsfvfnrclipxfqf extensions (#68297)
2023-11-03 10:52:37 +08:00
sf_vfwmacc_4x4x4.ll
[RISCV] Support Xsfvfwmaccqqq extensions (#68296)
2023-11-03 10:08:26 +08:00
sf_vqmacc_2x8x2.ll
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
2023-10-20 11:16:20 +08:00
sf_vqmacc_4x8x4.ll
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
2023-10-20 11:16:20 +08:00
sf_vqmaccsu_2x8x2.ll
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
2023-10-20 11:16:20 +08:00
sf_vqmaccsu_4x8x4.ll
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
2023-10-20 11:16:20 +08:00
sf_vqmaccu_2x8x2.ll
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
2023-10-20 11:16:20 +08:00
sf_vqmaccu_4x8x4.ll
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
2023-10-20 11:16:20 +08:00
sf_vqmaccus_2x8x2.ll
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
2023-10-20 11:16:20 +08:00
sf_vqmaccus_4x8x4.ll
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
2023-10-20 11:16:20 +08:00
shuffle-reverse.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
sink-splat-operands-i1.ll
[RISCV] Don't sink i1 vectors in shouldSinkOperands.
2023-07-06 20:36:55 -07:00
sink-splat-operands.ll
[RISCVInsertVSETVLI] Allow PRE with non-immediate AVLs (#71728)
2023-11-09 08:03:13 -08:00
smulo-sdnode.ll
…
splat-vector-split-i64-vl-sdnode.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
splat-vectors.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
splats-with-mixed-vl.ll
[DAG] Restrict insert_subvector undef, splat_veector, dontcare transform
2023-08-18 12:44:09 -07:00
sshl_sat_vec.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
stack-coloring-scalablevec.mir
…
stepvector.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
strided-load-store-intrinsics.ll
[RISCV] Add a combine to form masked.store from unit strided store
2023-09-19 07:45:35 -07:00
strided-load-store.ll
[RISCVGatherScatterLowering] Use InstSimplifyFolder
2023-05-12 17:33:07 -07:00
strided-vpload.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
strided-vpstore.ll
[DAGCombiner] Combine vp.strided.store with unit stride to vp.store (#66774)
2023-09-19 16:43:50 +01:00
subregister-undef-early-clobber.mir
[RISCVRVVInitUndef] Ignore tied use for partial undef register
2023-08-01 12:16:26 -07:00
tail-agnostic-impdef-copy.mir
…
umulo-sdnode.ll
…
unaligned-loads-stores.ll
[RISCV] Revise check names for unaligned memory op tests [nfc]
2023-07-20 13:36:53 -07:00
undef-earlyclobber-chain.ll
[RISCVRVVInitUndef] Ignore tied use for partial undef register
2023-08-01 12:16:26 -07:00
undef-earlyclobber-chain.mir
[RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF (try 2)
2023-08-01 10:50:03 -07:00
undef-vp-ops.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
unmasked-ta.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
unmasked-tu.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
urem-seteq-vec.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
ushl_sat_vec.ll
…
vaadd.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vaaddu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vadc.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vadd-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vadd-vp-mask.ll
[RISCV] Move some vector tests to rvv directory. NFC
2023-04-06 10:28:41 +01:00
vadd-vp.ll
…
vadd.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vaesdf.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vaesdm.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vaesef.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vaesem.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vaeskf1.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vaeskf2.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vaesz.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vand-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vand-vp.ll
…
vand.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vandn-sdnode.ll
[RISCV] Relax some Zvbb patterns and lowerings to Zvkb (#68115)
2023-10-03 17:42:40 +01:00
vandn-vp.ll
[RISCV] Relax some Zvbb patterns and lowerings to Zvkb (#68115)
2023-10-03 17:42:40 +01:00
vandn.ll
[RISCV] Bump vector crypto to v1.0 RC2
2023-08-17 21:19:59 -07:00
variant-cc.ll
…
vasub.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vasubu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vbrev8.ll
[RISCV] Bump vector crypto to v1.0 RC2
2023-08-17 21:19:59 -07:00
vbrev.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vclmul.ll
[RISCV] Add missing mask operand for masked vclmul/vclmulh tests. NFC.
2023-08-28 17:36:38 +08:00
vclmulh.ll
[RISCV] Add missing mask operand for masked vclmul/vclmulh tests. NFC.
2023-08-28 17:36:38 +08:00
vclz.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vcompress.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vcopysign-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vcpop.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vcpopv.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vctz.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vdiv-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
vdiv-vp.ll
…
vdiv.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vdivu-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
vdivu-vp.ll
…
vdivu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vec3-setcc-crash.ll
[RISCV] Move some vector tests to rvv directory. NFC
2023-04-06 10:28:41 +01:00
vector-deinterleave-fixed.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
vector-deinterleave-load.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vector-deinterleave.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vector-interleave-fixed.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
vector-interleave-store.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vector-interleave.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vector-splice.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vexts-sdnode.ll
…
vfabs-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfabs-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfadd-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfadd-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfadd-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfadd.ll
[RISCV] Add Zvfhmin extension support for llvm RISCV backend
2023-08-23 16:47:47 +08:00
vfclass-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfclass-vp.ll
[VP][RISCV] Add vp.is.fpclass and RISC-V support
2023-08-25 15:40:55 +08:00
vfclass.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfcmp-constrained-sdnode.ll
[RISCV] Add isCommutable for pseudos without merge operand
2023-08-29 15:51:17 +08:00
vfcmps-constrained-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfcopysign-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfcvt-f-x.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfcvt-f-xu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfcvt-rtz-x-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfcvt-rtz-xu-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfcvt-x-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfcvt-xu-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfdiv-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfdiv-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfdiv-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfdiv.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfirst.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfma-vp-combine.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfma-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfmacc-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfmacc.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfmadd-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfmadd-sdnode.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfmadd.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfmax-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfmax-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfmax.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfmerge.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfmin-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfmin-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfmin.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfmsac-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfmsac.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfmsub-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfmsub-sdnode.ll
[TwoAddressInstruction] Handle physical registers with LiveIntervals (#66784)
2023-10-19 16:26:30 +01:00
vfmsub.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfmul-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfmul-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfmul-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfmul.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfmuladd-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfmv.f.s.ll
[RISCV] Reduce LMUL for vector extracts
2023-08-22 07:36:17 -07:00
vfmv.s.f.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfmv.v.f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfncvt-f-f.ll
[RISCV] Add Zvfhmin extension support for llvm RISCV backend
2023-08-23 16:47:47 +08:00
vfncvt-f-x.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfncvt-f-xu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfncvt-rod-f-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfncvt-rtz-x-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfncvt-rtz-xu-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfncvt-x-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfncvt-xu-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfncvtbf16-f-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfneg-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfneg-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfnmacc-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfnmacc.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfnmadd-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfnmadd-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfnmadd.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfnmsac-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfnmsac.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfnmsub-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfnmsub-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfnmsub.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfpext-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
vfpext-sdnode.ll
[RISCV] Add Zvfhmin extension support for llvm RISCV backend
2023-08-23 16:47:47 +08:00
vfpext-vp.ll
[RISCV] Add Zvfhmin extension support for llvm RISCV backend
2023-08-23 16:47:47 +08:00
vfptoi-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
vfptoi-sdnode.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
vfptosi-vp-mask.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
vfptosi-vp.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
vfptoui-vp-mask.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
vfptoui-vp.ll
[RISCV] Support fptoi like ops for fp16 vectors input when only have Zvfhmin (#67532)
2023-10-08 10:44:19 +08:00
vfptrunc-constrained-sdnode.ll
[RISCV] Support STRICT_FP_ROUND and STRICT_FP_EXTEND when only have Zvfhmin (#68559)
2023-10-17 10:10:19 +08:00
vfptrunc-sdnode.ll
[RISCV] Add Zvfhmin extension support for llvm RISCV backend
2023-08-23 16:47:47 +08:00
vfptrunc-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfrdiv-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfrdiv.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfrec7.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfredmax.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfredmin.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfredosum.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfredusum.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfrsqrt7.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfrsub-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfrsub.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfsgnj.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfsgnjn.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfsgnjx.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfslide1down.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfslide1up.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfsqrt-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfsqrt-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfsqrt-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfsqrt.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfsub-constrained-sdnode.ll
[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)
2023-11-09 09:55:48 +08:00
vfsub-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfsub-vp.ll
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
2023-09-22 16:30:43 +01:00
vfsub.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwadd-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfwadd-vp.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfwadd.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwadd.w.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwcvt-f-f.ll
[RISCV] Add Zvfhmin extension support for llvm RISCV backend
2023-08-23 16:47:47 +08:00
vfwcvt-f-x.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwcvt-f-xu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwcvt-rtz-x-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwcvt-rtz-xu-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwcvt-x-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwcvt-xu-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwcvtbf16-f-f.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwmacc-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfwmacc-vp.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfwmacc.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwmaccbf16.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwmsac-vp.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vfwmsac.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwmul-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfwmul.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwnmacc-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfwnmacc.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwnmsac-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vfwnmsac.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwredosum.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwredusum.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwsub-sdnode.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vfwsub.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vfwsub.w.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vghsh.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vgmul.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vid.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
viota.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vitofp-constrained-sdnode.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
vitofp-sdnode.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vle_vid-vfcvt.ll
…
vle.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vleff-vlseg2ff-output.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
vleff.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vlm.ll
…
vloxei-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vloxei.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vloxseg-rv32.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vloxseg-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vlse.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vlseg-rv32.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vlseg-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vlsegff-rv32-dead.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vlsegff-rv32.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vlsegff-rv64-dead.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vlsegff-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vlsseg-rv32.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vlsseg-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vluxei-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vluxei.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vluxseg-rv32.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vluxseg-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vmacc-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vmacc.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmadc.carry.in.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmadc.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmadd-sdnode.ll
…
vmadd-vp.ll
[RISCV] Add tests for vmadd for VP intrinsics. NFC (#70042)
2023-10-26 07:59:25 +01:00
vmadd.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmand.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmandn.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmarith-sdnode.ll
…
vmax-sdnode.ll
…
vmax-vp.ll
…
vmax.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmaxu-sdnode.ll
…
vmaxu-vp.ll
…
vmaxu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmclr.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmerge.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmfeq.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmfge.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmfgt.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmfle.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmflt.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmfne.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmin-sdnode.ll
…
vmin-vp.ll
…
vmin.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vminu-sdnode.ll
…
vminu-vp.ll
…
vminu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmnand.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmnor.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmor.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmorn.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsbc.borrow.in.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsbc.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsbf.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmseq.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmset.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsge.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsgeu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsgt.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsgtu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsif.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsle.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsleu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmslt.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsltu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsne.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmsof.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmul-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vmul-vp-mask.ll
[RISCV] Move some vector tests to rvv directory. NFC
2023-04-06 10:28:41 +01:00
vmul-vp.ll
…
vmul.ll
[RISCV] Refactor predicates for rvv intrinsic patterns.
2023-05-17 09:47:52 +08:00
vmulh-sdnode.ll
[RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419)
2023-09-27 19:53:50 +01:00
vmulh.ll
[RISCV] Refactor predicates for rvv intrinsic patterns.
2023-05-17 09:47:52 +08:00
vmulhsu.ll
[RISCV] Refactor predicates for rvv intrinsic patterns.
2023-05-17 09:47:52 +08:00
vmulhu-sdnode.ll
[RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419)
2023-09-27 19:53:50 +01:00
vmulhu.ll
[RISCV] Refactor predicates for rvv intrinsic patterns.
2023-05-17 09:47:52 +08:00
vmv-copy.mir
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
vmv.s.x-rv32.ll
[RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (#66659)
2023-10-20 14:19:04 -04:00
vmv.s.x-rv64.ll
[RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (#66659)
2023-10-20 14:19:04 -04:00
vmv.v.v-rv32.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmv.v.v-rv64.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmv.v.x-rv32.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmv.v.x-rv64.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmv.x.s-rv32.ll
[RISCVInsertVSETVLI] Default to VL=1 for scalar extracts
2023-08-16 07:35:00 -07:00
vmv.x.s-rv64.ll
[RISCVInsertVSETVLI] Default to VL=1 for scalar extracts
2023-08-16 07:35:00 -07:00
vmxnor.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vmxor.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vnclip.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vnclipu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vnmsac-vp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vnmsac.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vnmsub-sdnode.ll
…
vnmsub.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vnsra-sdnode.ll
[RISCV] Add patterns for vnsr[a,l].wx where shift amount has different type than vector element
2023-07-21 10:13:28 +01:00
vnsra-vp.ll
[RISCV] Match ext_vl+sra_vl/srl_vl+trunc_vector_vl to vnsra.wv/vnsrl.wv
2023-07-25 14:21:02 +08:00
vnsra.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vnsrl-sdnode.ll
[DAGCombiner] Combine trunc (splat_vector x) -> splat_vector (trunc x)
2023-08-30 15:22:57 +01:00
vnsrl-vp.ll
[RISCV] Match ext_vl+sra_vl/srl_vl+trunc_vector_vl to vnsra.wv/vnsrl.wv
2023-07-25 14:21:02 +08:00
vnsrl.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vor-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vor-vp.ll
…
vor.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vp-reverse-float-fixed-vectors.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vp-reverse-float.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vp-reverse-int-fixed-vectors.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vp-reverse-int.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vp-reverse-mask-fixed-vectors.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vp-reverse-mask.ll
[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)
2023-11-05 22:39:27 -08:00
vpgather-sdnode.ll
[RISCV] Move narrowIndex to be a DAG combine over target independent nodes
2023-09-15 15:02:14 -07:00
vpload.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
vpmerge-sdnode.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vpscatter-sdnode.ll
[RISCV] Move narrowIndex to be a DAG combine over target independent nodes
2023-09-15 15:02:14 -07:00
vpstore.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
vredand.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vredmax.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vredmaxu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vredmin.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vredminu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vredor.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vredsum.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vreductions-fp-sdnode.ll
[RISCVInsertVSETVLI] Default to VL=1 for scalar extracts
2023-08-16 07:35:00 -07:00
vreductions-fp-vp.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
vreductions-int-vp.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
vreductions-int.ll
[RISCVInsertVSETVLI] Handle vl-preserve case in backwards rewrite
2023-08-21 12:28:28 -07:00
vreductions-mask-vp.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
vreductions-mask.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
vredxor.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vrem-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
vrem-vp.ll
…
vrem.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vremu-sdnode.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
vremu-vp.ll
…
vremu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vrev8.ll
[RISCV] Bump vector crypto to v1.0 RC2
2023-08-17 21:19:59 -07:00
vrgather-rv32.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vrgather-rv64.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vrgatherei16-rv32.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vrgatherei16-rv64.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vrgatherei16-subreg-liveness.ll
…
vrol-sdnode.ll
[RISCV] Relax some Zvbb patterns and lowerings to Zvkb (#68115)
2023-10-03 17:42:40 +01:00
vrol.ll
[RISCV] Bump vector crypto to v1.0 RC2
2023-08-17 21:19:59 -07:00
vror-sdnode.ll
[RISCV] Relax some Zvbb patterns and lowerings to Zvkb (#68115)
2023-10-03 17:42:40 +01:00
vror.ll
[RISCV] Bump vector crypto to v1.0 RC2
2023-08-17 21:19:59 -07:00
vrsub-sdnode.ll
…
vrsub-vp.ll
…
vrsub.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsadd-rv32.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsadd-rv64.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsadd-sdnode.ll
…
vsaddu-rv32.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsaddu-rv64.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsaddu-sdnode.ll
…
vsbc.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vscale-power-of-two.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vse.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vselect-fp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vselect-int.ll
…
vselect-mask.ll
…
vselect-vp.ll
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
vsetvl-ext.ll
…
vsetvli-insert-crossbb.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
vsetvli-insert-crossbb.mir
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
vsetvli-insert.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vsetvli-insert.mir
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
vsetvli-intrinsics.ll
[RISCV] Use x0 in vsetvli when avl is equal to vlmax.
2023-07-31 09:49:40 +08:00
vsetvli-regression.ll
[RISCVInsertVSETVLI] Default to VL=1 for scalar extracts
2023-08-16 07:35:00 -07:00
vsetvli-valid-elen-fp.ll
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
vsext-vp-mask.ll
…
vsext-vp.ll
…
vsext.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsha2ch.ll
[RISCV] Fix wrong implication for zvknhb. (#66860)
2023-11-03 09:32:21 +08:00
vsha2cl.ll
[RISCV] Fix wrong implication for zvknhb. (#66860)
2023-11-03 09:32:21 +08:00
vsha2ms.ll
[RISCV] Fix wrong implication for zvknhb. (#66860)
2023-11-03 09:32:21 +08:00
vshl-sdnode.ll
…
vshl-vp.ll
…
vsitofp-vp-mask.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vsitofp-vp.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vslide1down-constant-vl-rv32.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
vslide1down-rv32.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vslide1down-rv64.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vslide1up-constant-vl-rv32.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
vslide1up-rv32.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vslide1up-rv64.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vslidedown.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vslideup.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsll.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsm3c.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vsm3me.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vsm4k.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vsm4r.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vsm.ll
…
vsmul-rv32.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vsmul-rv64.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vsoxei-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vsoxei.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsoxseg-rv32.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vsoxseg-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vsplats-fp.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vsplats-i1.ll
Reapply "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
2023-05-10 11:51:51 -07:00
vsplats-i64.ll
…
vsplats-zfa.ll
[RISCV] Mark the Zfa extension as non-experimental (#68113)
2023-10-03 18:16:13 +01:00
vsra-sdnode.ll
[RISCV] Combine trunc (sra sext (x), zext (y)) to sra (x, smin (y, scalarsizeinbits(y) - 1)) (#65728)
2023-09-17 17:11:28 +08:00
vsra-vp.ll
…
vsra.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsrl-sdnode.ll
…
vsrl-vp.ll
…
vsrl.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsse.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsseg-rv32.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vsseg-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vssra-rv32.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vssra-rv64.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vssrl-rv32.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vssrl-rv64.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vssseg-rv32.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vssseg-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vssub-rv32.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vssub-rv64.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vssub-sdnode.ll
…
vssubu-rv32.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vssubu-rv64.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vssubu-sdnode.ll
…
vsub-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vsub-vp-mask.ll
[RISCV] Move some vector tests to rvv directory. NFC
2023-04-06 10:28:41 +01:00
vsub-vp.ll
…
vsub.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsuxei-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vsuxei.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vsuxseg-rv32.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vsuxseg-rv64.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vtrunc-vp-mask.ll
…
vtrunc-vp.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vtruncs-sdnode.ll
…
vuitofp-vp-mask.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
vuitofp-vp.ll
[RISCV] Apply promotion for f16 vector ops when only have zvfhmin
2023-08-23 16:49:20 +08:00
vwadd-sdnode.ll
…
vwadd-vp.ll
…
vwadd.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwadd.w.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwaddu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwaddu.w.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwmacc-sdnode.ll
…
vwmacc-vp.ll
[RISCV] Add some tail undisturbed vwmacc tests. NFC
2023-05-30 15:16:00 -07:00
vwmacc.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwmaccsu-vp.ll
[RISCV] Introduce RISCVISD::VWMACC(U/SU)_VL opcode
2023-06-16 16:11:35 -07:00
vwmaccsu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwmaccu-vp.ll
[RISCV] Add some tail undisturbed vwmacc tests. NFC
2023-05-30 15:16:00 -07:00
vwmaccu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwmaccus.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwmul-sdnode.ll
…
vwmul.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwmulsu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwmulu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwredsum.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwredsumu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwsll-sdnode.ll
[DAGCombiner] Combine trunc (splat_vector x) -> splat_vector (trunc x)
2023-08-30 15:22:57 +01:00
vwsll-vp.ll
[DAGCombiner] Combine trunc (splat_vector x) -> splat_vector (trunc x)
2023-08-30 15:22:57 +01:00
vwsll.ll
[RISCV] Support vector crypto extension LLVM IR
2023-08-02 10:25:36 -07:00
vwsub-sdnode.ll
…
vwsub.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwsub.w.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwsubu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vwsubu.w.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vxor-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vxor-vp.ll
…
vxor.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
vxrm-insert.ll
[RISCV] Implement cross basic block VXRM write insertion. (#70382)
2023-11-02 14:09:27 -07:00
vxrm.mir
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
vzext-vp-mask.ll
…
vzext-vp.ll
…
vzext.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
wrong-chain-fixed-load.ll
[RISCV] Remove -riscv-v-vector-bits-min in tests. NFC (#65404)
2023-09-06 10:43:41 +01:00
wrong-stack-offset-for-rvv-object.mir
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
wrong-stack-slot-rv32.mir
…
wrong-stack-slot-rv64.mir
…
xsfvcp-x.ll
[RISCV] Support floating point VCIX (#67094)
2023-09-25 13:19:21 +08:00
xsfvcp-xv.ll
[RISCV] Support floating point VCIX (#67094)
2023-09-25 13:19:21 +08:00
xsfvcp-xvv.ll
[RISCV] Support floating point VCIX (#67094)
2023-09-25 13:19:21 +08:00
xsfvcp-xvw.ll
[RISCV] Support floating point VCIX (#67094)
2023-09-25 13:19:21 +08:00
xtheadvdot-vmaqa.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
xtheadvdot-vmaqasu.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
xtheadvdot-vmaqau.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
xtheadvdot-vmaqaus.ll
[RISCV] Add a blank line after end of RUN lines. NFC.
2023-08-07 18:38:09 +08:00
zve32-types.ll
…
zvlsseg-copy.mir
…
zvlsseg-spill.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
zvlsseg-zero-vl.ll
…