3de645efe3
Before we tracked the size of the teams reduction buffer in order to allocate it at runtime per kernel launch. This patch splits the number into two parts, the size of the reduction data (=all reduction variables) and the (maximal) length of the buffer. This will allow us to allocate less if we need less, e.g., if we have less teams than the maximal length. It also allows us to move code from clangs codegen into the runtime as we now know how large the reduction data is.
4194 lines
250 KiB
LLVM
4194 lines
250 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs
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; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU
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; RUN: opt --mtriple=nvptx64-- -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=NVPTX
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; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -openmp-opt-disable-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU-DISABLED
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; RUN: opt --mtriple=nvptx64-- -openmp-opt-disable-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=NVPTX-DISABLED
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;; void p0(void);
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;; void p1(void);
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;; int unknown(void);
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;; void unknown_pure(void) __attribute__((pure));
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;; void unknown_no_openmp(void) __attribute__((assume("omp_no_openmp")));
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;;
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;; int G;
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;; void no_parallel_region_in_here(void) {
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;; #pragma omp single
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;; G = 0;
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;; }
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;;
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;; void no_state_machine_needed() {
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;; #pragma omp target teams
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;; {
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;; no_parallel_region_in_here();
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;; unknown_no_openmp();
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;; }
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;; }
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;;
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;; void simple_state_machine() {
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;; #pragma omp target teams
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;; {
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;; unknown_no_openmp();
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;; #pragma omp parallel
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;; { p0(); }
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;; no_parallel_region_in_here();
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;; #pragma omp parallel
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;; { p1(); }
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;; }
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;; }
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;;
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;; void simple_state_machine_interprocedural_after(void);
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;; void simple_state_machine_interprocedural_before(void) {
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;; #pragma omp parallel
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;; { p0(); }
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;; }
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;; void simple_state_machine_interprocedural() {
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;; #pragma omp target teams
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;; {
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;; unknown_no_openmp();
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;; simple_state_machine_interprocedural_before();
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;; no_parallel_region_in_here();
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;; #pragma omp parallel
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;; { p1(); }
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;; simple_state_machine_interprocedural_after();
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;; }
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;; }
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;; void simple_state_machine_interprocedural_after(void) {
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;; #pragma omp parallel
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;; { p0(); }
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;; }
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;;
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;; void simple_state_machine_with_fallback() {
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;; #pragma omp target teams
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;; {
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;; #pragma omp parallel
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;; { p0(); }
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;; unknown();
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;; #pragma omp parallel
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;; { p1(); }
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;; }
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;; }
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;;
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;; void simple_state_machine_no_openmp_attr() {
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;; #pragma omp target teams
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;; {
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;; #pragma omp parallel
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;; { p0(); }
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;; unknown_no_openmp();
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;; #pragma omp parallel
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;; { p1(); }
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;; }
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;; }
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;;
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;; void simple_state_machine_pure() {
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;; #pragma omp target teams
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;; {
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;; unknown_no_openmp();
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;; #pragma omp parallel
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;; { p0(); }
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;; unknown_pure();
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;; #pragma omp parallel
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;; { p1(); }
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;; }
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;; }
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;;
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;; int omp_get_thread_num();
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;; void simple_state_machine_interprocedural_nested_recursive_after(int);
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;; void simple_state_machine_interprocedural_nested_recursive_after_after(void);
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;; void simple_state_machine_interprocedural_nested_recursive() {
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;; #pragma omp target teams
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;; {
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;; simple_state_machine_interprocedural_nested_recursive_after(
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;; omp_get_thread_num());
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;; }
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;; }
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;;
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;; void simple_state_machine_interprocedural_nested_recursive_after(int a) {
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;; if (a == 0)
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;; return;
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;; simple_state_machine_interprocedural_nested_recursive_after(a - 1);
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;; simple_state_machine_interprocedural_nested_recursive_after_after();
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;; }
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;; void simple_state_machine_interprocedural_nested_recursive_after_after(void) {
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;; #pragma omp parallel
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;; { p0(); }
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;; }
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;;
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;; __attribute__((weak)) void weak_callee_empty(void) {}
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;; void no_state_machine_weak_callee() {
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;; #pragma omp target teams
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;; { weak_callee_empty(); }
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;; }
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%struct.ident_t = type { i32, i32, i32, i32, ptr }
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%struct.KernelEnvironmentTy = type { %struct.ConfigurationEnvironmentTy, ptr, ptr }
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%struct.ConfigurationEnvironmentTy = type { i8, i8, i8, i32, i32, i32, i32, i32, i32 }
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@0 = private unnamed_addr constant [23 x i8] c";unknown;unknown;0;0;;\00", align 1
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@1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @0 }, align 8
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@2 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 2, i32 0, ptr @0 }, align 8
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@G = external global i32, align 4
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@3 = private unnamed_addr constant %struct.ident_t { i32 0, i32 322, i32 2, i32 0, ptr @0 }, align 8
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@__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @1, ptr null }
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@__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @1, ptr null }
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@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @1, ptr null }
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@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @1, ptr null }
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@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @1, ptr null }
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@__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @1, ptr null }
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@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @1, ptr null }
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@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @1, ptr null }
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define weak void @__omp_offloading_14_a36502b_no_state_machine_needed_l14(ptr %dyn) #0 {
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entry:
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%.zero.addr = alloca i32, align 4
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%.threadid_temp. = alloca i32, align 4
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store i32 0, ptr %.zero.addr, align 4
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%0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment, ptr %dyn)
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%exec_user_code = icmp eq i32 %0, -1
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br i1 %exec_user_code, label %user_code.entry, label %worker.exit
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user_code.entry: ; preds = %entry
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%1 = call i32 @__kmpc_global_thread_num(ptr @1)
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store i32 %1, ptr %.threadid_temp., align 4
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call void @__omp_outlined__(ptr %.threadid_temp., ptr %.zero.addr) #3
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call void @__kmpc_target_deinit()
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ret void
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worker.exit: ; preds = %entry
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ret void
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}
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; Make it a weak definition so we will apply custom state machine rewriting but can't use the body in the reasoning.
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define weak i32 @__kmpc_target_init(ptr, ptr) {
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ret i32 0
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}
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define internal void @__omp_outlined__(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
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entry:
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%.global_tid..addr = alloca ptr, align 8
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%.bound_tid..addr = alloca ptr, align 8
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store ptr %.global_tid., ptr %.global_tid..addr, align 8
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store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
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call void @no_parallel_region_in_here() #7
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call void @unknown_no_openmp() #8
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ret void
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}
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define hidden void @no_parallel_region_in_here() #1 {
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entry:
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%0 = call i32 @__kmpc_global_thread_num(ptr @2)
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%1 = call i32 @__kmpc_single(ptr @2, i32 %0)
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%2 = icmp ne i32 %1, 0
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br i1 %2, label %omp_if.then, label %omp_if.end
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omp_if.then: ; preds = %entry
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store i32 0, ptr @G, align 4
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call void @__kmpc_end_single(ptr @2, i32 %0)
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br label %omp_if.end
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omp_if.end: ; preds = %omp_if.then, %entry
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call void @__kmpc_barrier(ptr @3, i32 %0)
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ret void
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}
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declare void @unknown_no_openmp() #2
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declare i32 @__kmpc_global_thread_num(ptr) #3
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declare void @__kmpc_target_deinit()
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define weak void @__omp_offloading_14_a36502b_simple_state_machine_l22(ptr %dyn) #0 {
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entry:
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%.zero.addr = alloca i32, align 4
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%.threadid_temp. = alloca i32, align 4
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store i32 0, ptr %.zero.addr, align 4
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%0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment, ptr %dyn)
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%exec_user_code = icmp eq i32 %0, -1
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br i1 %exec_user_code, label %user_code.entry, label %worker.exit
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user_code.entry: ; preds = %entry
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%1 = call i32 @__kmpc_global_thread_num(ptr @1)
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store i32 %1, ptr %.threadid_temp., align 4
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call void @__omp_outlined__1(ptr %.threadid_temp., ptr %.zero.addr) #3
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call void @__kmpc_target_deinit()
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ret void
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worker.exit: ; preds = %entry
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ret void
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}
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define internal void @__omp_outlined__1(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
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entry:
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%.global_tid..addr = alloca ptr, align 8
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%.bound_tid..addr = alloca ptr, align 8
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%captured_vars_addrs = alloca [0 x ptr], align 8
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%captured_vars_addrs1 = alloca [0 x ptr], align 8
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store ptr %.global_tid., ptr %.global_tid..addr, align 8
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store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
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call void @unknown_no_openmp() #8
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%0 = load ptr, ptr %.global_tid..addr, align 8
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%1 = load i32, ptr %0, align 4
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call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr %captured_vars_addrs, i64 0)
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call void @no_parallel_region_in_here() #7
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call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr %captured_vars_addrs1, i64 0)
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ret void
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}
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define internal void @__omp_outlined__2(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
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entry:
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%.global_tid..addr = alloca ptr, align 8
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%.bound_tid..addr = alloca ptr, align 8
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store ptr %.global_tid., ptr %.global_tid..addr, align 8
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store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
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call void @p0() #7
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ret void
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}
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declare void @p0() #4
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define internal void @__omp_outlined__2_wrapper(i16 zeroext %0, i32 %1) #0 {
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entry:
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%.addr = alloca i16, align 2
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%.addr1 = alloca i32, align 4
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%.zero.addr = alloca i32, align 4
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%global_args = alloca ptr, align 8
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store i32 0, ptr %.zero.addr, align 4
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store i16 %0, ptr %.addr, align 2
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store i32 %1, ptr %.addr1, align 4
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call void @__kmpc_get_shared_variables(ptr %global_args)
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call void @__omp_outlined__2(ptr %.addr1, ptr %.zero.addr) #3
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ret void
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}
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declare void @__kmpc_get_shared_variables(ptr)
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declare void @__kmpc_parallel_51(ptr, i32, i32, i32, i32, ptr, ptr, ptr, i64)
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define internal void @__omp_outlined__3(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
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entry:
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%.global_tid..addr = alloca ptr, align 8
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%.bound_tid..addr = alloca ptr, align 8
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store ptr %.global_tid., ptr %.global_tid..addr, align 8
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store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
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call void @p1() #7
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ret void
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}
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declare void @p1() #4
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define internal void @__omp_outlined__3_wrapper(i16 zeroext %0, i32 %1) #0 {
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entry:
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%.addr = alloca i16, align 2
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%.addr1 = alloca i32, align 4
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%.zero.addr = alloca i32, align 4
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%global_args = alloca ptr, align 8
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store i32 0, ptr %.zero.addr, align 4
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store i16 %0, ptr %.addr, align 2
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store i32 %1, ptr %.addr1, align 4
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call void @__kmpc_get_shared_variables(ptr %global_args)
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call void @__omp_outlined__3(ptr %.addr1, ptr %.zero.addr) #3
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ret void
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}
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define weak void @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39(ptr %dyn) #0 {
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|
entry:
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|
%.zero.addr = alloca i32, align 4
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|
%.threadid_temp. = alloca i32, align 4
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|
store i32 0, ptr %.zero.addr, align 4
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|
%0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment, ptr %dyn)
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%exec_user_code = icmp eq i32 %0, -1
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br i1 %exec_user_code, label %user_code.entry, label %worker.exit
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user_code.entry: ; preds = %entry
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%1 = call i32 @__kmpc_global_thread_num(ptr @1)
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store i32 %1, ptr %.threadid_temp., align 4
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call void @__omp_outlined__4(ptr %.threadid_temp., ptr %.zero.addr) #3
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call void @__kmpc_target_deinit()
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ret void
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worker.exit: ; preds = %entry
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ret void
|
|
}
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|
|
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define internal void @__omp_outlined__4(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
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|
%.global_tid..addr = alloca ptr, align 8
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|
%.bound_tid..addr = alloca ptr, align 8
|
|
%captured_vars_addrs = alloca [0 x ptr], align 8
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|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
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store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
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call void @unknown_no_openmp() #8
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call void @simple_state_machine_interprocedural_before() #7
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call void @no_parallel_region_in_here() #7
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%0 = load ptr, ptr %.global_tid..addr, align 8
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%1 = load i32, ptr %0, align 4
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call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr %captured_vars_addrs, i64 0)
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call void @simple_state_machine_interprocedural_after() #7
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ret void
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|
}
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define hidden void @simple_state_machine_interprocedural_before() #1 {
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|
entry:
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%captured_vars_addrs = alloca [0 x ptr], align 8
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%0 = call i32 @__kmpc_global_thread_num(ptr @2)
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call void @__kmpc_parallel_51(ptr @2, i32 %0, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr %captured_vars_addrs, i64 0)
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|
ret void
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|
}
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|
|
|
define internal void @__omp_outlined__5(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
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|
%.global_tid..addr = alloca ptr, align 8
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|
%.bound_tid..addr = alloca ptr, align 8
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|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
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|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
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|
call void @p1() #7
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ret void
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|
}
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|
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|
define internal void @__omp_outlined__5_wrapper(i16 zeroext %0, i32 %1) #0 {
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|
entry:
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|
%.addr = alloca i16, align 2
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|
%.addr1 = alloca i32, align 4
|
|
%.zero.addr = alloca i32, align 4
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|
%global_args = alloca ptr, align 8
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|
store i32 0, ptr %.zero.addr, align 4
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|
store i16 %0, ptr %.addr, align 2
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store i32 %1, ptr %.addr1, align 4
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|
call void @__kmpc_get_shared_variables(ptr %global_args)
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call void @__omp_outlined__5(ptr %.addr1, ptr %.zero.addr) #3
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ret void
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|
}
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define hidden void @simple_state_machine_interprocedural_after() #1 {
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|
entry:
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|
%captured_vars_addrs = alloca [0 x ptr], align 8
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%0 = call i32 @__kmpc_global_thread_num(ptr @2)
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call void @__kmpc_parallel_51(ptr @2, i32 %0, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr %captured_vars_addrs, i64 0)
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ret void
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|
}
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|
|
|
define weak void @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55(ptr %dyn) #0 {
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|
entry:
|
|
%.zero.addr = alloca i32, align 4
|
|
%.threadid_temp. = alloca i32, align 4
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
%0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment, ptr %dyn)
|
|
%exec_user_code = icmp eq i32 %0, -1
|
|
br i1 %exec_user_code, label %user_code.entry, label %worker.exit
|
|
|
|
user_code.entry: ; preds = %entry
|
|
%1 = call i32 @__kmpc_global_thread_num(ptr @1)
|
|
store i32 %1, ptr %.threadid_temp., align 4
|
|
call void @__omp_outlined__6(ptr %.threadid_temp., ptr %.zero.addr) #3
|
|
call void @__kmpc_target_deinit()
|
|
ret void
|
|
|
|
worker.exit: ; preds = %entry
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__6(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
%captured_vars_addrs = alloca [0 x ptr], align 8
|
|
%captured_vars_addrs1 = alloca [0 x ptr], align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
%0 = load ptr, ptr %.global_tid..addr, align 8
|
|
%1 = load i32, ptr %0, align 4
|
|
call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr %captured_vars_addrs, i64 0)
|
|
%call = call i32 @unknown() #7
|
|
call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr %captured_vars_addrs1, i64 0)
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__7(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @p0() #7
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__7_wrapper(i16 zeroext %0, i32 %1) #0 {
|
|
entry:
|
|
%.addr = alloca i16, align 2
|
|
%.addr1 = alloca i32, align 4
|
|
%.zero.addr = alloca i32, align 4
|
|
%global_args = alloca ptr, align 8
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
store i16 %0, ptr %.addr, align 2
|
|
store i32 %1, ptr %.addr1, align 4
|
|
call void @__kmpc_get_shared_variables(ptr %global_args)
|
|
call void @__omp_outlined__7(ptr %.addr1, ptr %.zero.addr) #3
|
|
ret void
|
|
}
|
|
|
|
declare i32 @unknown() #4
|
|
|
|
define internal void @__omp_outlined__8(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @p1() #7
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__8_wrapper(i16 zeroext %0, i32 %1) #0 {
|
|
entry:
|
|
%.addr = alloca i16, align 2
|
|
%.addr1 = alloca i32, align 4
|
|
%.zero.addr = alloca i32, align 4
|
|
%global_args = alloca ptr, align 8
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
store i16 %0, ptr %.addr, align 2
|
|
store i32 %1, ptr %.addr1, align 4
|
|
call void @__kmpc_get_shared_variables(ptr %global_args)
|
|
call void @__omp_outlined__8(ptr %.addr1, ptr %.zero.addr) #3
|
|
ret void
|
|
}
|
|
|
|
define weak void @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66(ptr %dyn) #0 {
|
|
entry:
|
|
%.zero.addr = alloca i32, align 4
|
|
%.threadid_temp. = alloca i32, align 4
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
%0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment, ptr %dyn)
|
|
%exec_user_code = icmp eq i32 %0, -1
|
|
br i1 %exec_user_code, label %user_code.entry, label %worker.exit
|
|
|
|
user_code.entry: ; preds = %entry
|
|
%1 = call i32 @__kmpc_global_thread_num(ptr @1)
|
|
store i32 %1, ptr %.threadid_temp., align 4
|
|
call void @__omp_outlined__9(ptr %.threadid_temp., ptr %.zero.addr) #3
|
|
call void @__kmpc_target_deinit()
|
|
ret void
|
|
|
|
worker.exit: ; preds = %entry
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__9(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
%captured_vars_addrs = alloca [0 x ptr], align 8
|
|
%captured_vars_addrs1 = alloca [0 x ptr], align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
%0 = load ptr, ptr %.global_tid..addr, align 8
|
|
%1 = load i32, ptr %0, align 4
|
|
call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr %captured_vars_addrs, i64 0)
|
|
call void @unknown_no_openmp() #8
|
|
call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr %captured_vars_addrs1, i64 0)
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__10(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @p0() #7
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__10_wrapper(i16 zeroext %0, i32 %1) #0 {
|
|
entry:
|
|
%.addr = alloca i16, align 2
|
|
%.addr1 = alloca i32, align 4
|
|
%.zero.addr = alloca i32, align 4
|
|
%global_args = alloca ptr, align 8
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
store i16 %0, ptr %.addr, align 2
|
|
store i32 %1, ptr %.addr1, align 4
|
|
call void @__kmpc_get_shared_variables(ptr %global_args)
|
|
call void @__omp_outlined__10(ptr %.addr1, ptr %.zero.addr) #3
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__11(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @p1() #7
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__11_wrapper(i16 zeroext %0, i32 %1) #0 {
|
|
entry:
|
|
%.addr = alloca i16, align 2
|
|
%.addr1 = alloca i32, align 4
|
|
%.zero.addr = alloca i32, align 4
|
|
%global_args = alloca ptr, align 8
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
store i16 %0, ptr %.addr, align 2
|
|
store i32 %1, ptr %.addr1, align 4
|
|
call void @__kmpc_get_shared_variables(ptr %global_args)
|
|
call void @__omp_outlined__11(ptr %.addr1, ptr %.zero.addr) #3
|
|
ret void
|
|
}
|
|
|
|
define weak void @__omp_offloading_14_a36502b_simple_state_machine_pure_l77(ptr %dyn) #0 {
|
|
entry:
|
|
%.zero.addr = alloca i32, align 4
|
|
%.threadid_temp. = alloca i32, align 4
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
%0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment, ptr %dyn)
|
|
%exec_user_code = icmp eq i32 %0, -1
|
|
br i1 %exec_user_code, label %user_code.entry, label %worker.exit
|
|
|
|
user_code.entry: ; preds = %entry
|
|
%1 = call i32 @__kmpc_global_thread_num(ptr @1)
|
|
store i32 %1, ptr %.threadid_temp., align 4
|
|
call void @__omp_outlined__12(ptr %.threadid_temp., ptr %.zero.addr) #3
|
|
call void @__kmpc_target_deinit()
|
|
ret void
|
|
|
|
worker.exit: ; preds = %entry
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__12(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
%captured_vars_addrs = alloca [0 x ptr], align 8
|
|
%captured_vars_addrs1 = alloca [0 x ptr], align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @unknown_no_openmp() #8
|
|
%0 = load ptr, ptr %.global_tid..addr, align 8
|
|
%1 = load i32, ptr %0, align 4
|
|
call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr %captured_vars_addrs, i64 0)
|
|
call void @unknown_pure() #9
|
|
call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr %captured_vars_addrs1, i64 0)
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__13(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @p0() #7
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__13_wrapper(i16 zeroext %0, i32 %1) #0 {
|
|
entry:
|
|
%.addr = alloca i16, align 2
|
|
%.addr1 = alloca i32, align 4
|
|
%.zero.addr = alloca i32, align 4
|
|
%global_args = alloca ptr, align 8
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
store i16 %0, ptr %.addr, align 2
|
|
store i32 %1, ptr %.addr1, align 4
|
|
call void @__kmpc_get_shared_variables(ptr %global_args)
|
|
call void @__omp_outlined__13(ptr %.addr1, ptr %.zero.addr) #3
|
|
ret void
|
|
}
|
|
|
|
declare void @unknown_pure() #5
|
|
|
|
define internal void @__omp_outlined__14(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @p1() #7
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__14_wrapper(i16 zeroext %0, i32 %1) #0 {
|
|
entry:
|
|
%.addr = alloca i16, align 2
|
|
%.addr1 = alloca i32, align 4
|
|
%.zero.addr = alloca i32, align 4
|
|
%global_args = alloca ptr, align 8
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
store i16 %0, ptr %.addr, align 2
|
|
store i32 %1, ptr %.addr1, align 4
|
|
call void @__kmpc_get_shared_variables(ptr %global_args)
|
|
call void @__omp_outlined__14(ptr %.addr1, ptr %.zero.addr) #3
|
|
ret void
|
|
}
|
|
|
|
define weak void @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92(ptr %dyn) #0 {
|
|
entry:
|
|
%.zero.addr = alloca i32, align 4
|
|
%.threadid_temp. = alloca i32, align 4
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
%0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment, ptr %dyn)
|
|
%exec_user_code = icmp eq i32 %0, -1
|
|
br i1 %exec_user_code, label %user_code.entry, label %worker.exit
|
|
|
|
user_code.entry: ; preds = %entry
|
|
%1 = call i32 @__kmpc_global_thread_num(ptr @1)
|
|
store i32 %1, ptr %.threadid_temp., align 4
|
|
call void @__omp_outlined__15(ptr %.threadid_temp., ptr %.zero.addr) #3
|
|
call void @__kmpc_target_deinit()
|
|
ret void
|
|
|
|
worker.exit: ; preds = %entry
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__15(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
%call = call i32 @omp_get_thread_num() #7
|
|
call void @simple_state_machine_interprocedural_nested_recursive_after(i32 %call) #7
|
|
ret void
|
|
}
|
|
|
|
define hidden void @simple_state_machine_interprocedural_nested_recursive_after(i32 %a) #1 {
|
|
entry:
|
|
%a.addr = alloca i32, align 4
|
|
store i32 %a, ptr %a.addr, align 4
|
|
%0 = load i32, ptr %a.addr, align 4
|
|
%cmp = icmp eq i32 %0, 0
|
|
br i1 %cmp, label %if.then, label %if.end
|
|
|
|
if.then: ; preds = %entry
|
|
br label %return
|
|
|
|
if.end: ; preds = %entry
|
|
%1 = load i32, ptr %a.addr, align 4
|
|
%sub = sub nsw i32 %1, 1
|
|
call void @simple_state_machine_interprocedural_nested_recursive_after(i32 %sub) #7
|
|
call void @simple_state_machine_interprocedural_nested_recursive_after_after() #7
|
|
br label %return
|
|
|
|
return: ; preds = %if.end, %if.then
|
|
ret void
|
|
}
|
|
|
|
declare i32 @omp_get_thread_num(...) #4
|
|
|
|
define weak void @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112(ptr %dyn) #0 {
|
|
entry:
|
|
%.zero.addr = alloca i32, align 4
|
|
%.threadid_temp. = alloca i32, align 4
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
%0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment, ptr %dyn)
|
|
%exec_user_code = icmp eq i32 %0, -1
|
|
br i1 %exec_user_code, label %user_code.entry, label %worker.exit
|
|
|
|
user_code.entry: ; preds = %entry
|
|
%1 = call i32 @__kmpc_global_thread_num(ptr @1)
|
|
store i32 %1, ptr %.threadid_temp., align 4
|
|
call void @__omp_outlined__16(ptr %.threadid_temp., ptr %.zero.addr) #3
|
|
call void @__kmpc_target_deinit()
|
|
ret void
|
|
|
|
worker.exit: ; preds = %entry
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__16(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @weak_callee_empty() #7
|
|
ret void
|
|
}
|
|
|
|
define weak hidden void @weak_callee_empty() #1 {
|
|
entry:
|
|
ret void
|
|
}
|
|
|
|
declare i32 @__kmpc_single(ptr, i32) #6
|
|
|
|
declare void @__kmpc_end_single(ptr, i32) #6
|
|
|
|
declare void @__kmpc_barrier(ptr, i32) #6
|
|
|
|
define internal void @__omp_outlined__17(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @p0() #7
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__17_wrapper(i16 zeroext %0, i32 %1) #0 {
|
|
entry:
|
|
%.addr = alloca i16, align 2
|
|
%.addr1 = alloca i32, align 4
|
|
%.zero.addr = alloca i32, align 4
|
|
%global_args = alloca ptr, align 8
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
store i16 %0, ptr %.addr, align 2
|
|
store i32 %1, ptr %.addr1, align 4
|
|
call void @__kmpc_get_shared_variables(ptr %global_args)
|
|
call void @__omp_outlined__17(ptr %.addr1, ptr %.zero.addr) #3
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__18(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @p0() #7
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__18_wrapper(i16 zeroext %0, i32 %1) #0 {
|
|
entry:
|
|
%.addr = alloca i16, align 2
|
|
%.addr1 = alloca i32, align 4
|
|
%.zero.addr = alloca i32, align 4
|
|
%global_args = alloca ptr, align 8
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
store i16 %0, ptr %.addr, align 2
|
|
store i32 %1, ptr %.addr1, align 4
|
|
call void @__kmpc_get_shared_variables(ptr %global_args)
|
|
call void @__omp_outlined__18(ptr %.addr1, ptr %.zero.addr) #3
|
|
ret void
|
|
}
|
|
|
|
define hidden void @simple_state_machine_interprocedural_nested_recursive_after_after() #1 {
|
|
entry:
|
|
%captured_vars_addrs = alloca [0 x ptr], align 8
|
|
%0 = call i32 @__kmpc_global_thread_num(ptr @2)
|
|
call void @__kmpc_parallel_51(ptr @2, i32 %0, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr %captured_vars_addrs, i64 0)
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__19(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
|
|
entry:
|
|
%.global_tid..addr = alloca ptr, align 8
|
|
%.bound_tid..addr = alloca ptr, align 8
|
|
store ptr %.global_tid., ptr %.global_tid..addr, align 8
|
|
store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
|
|
call void @p0() #7
|
|
ret void
|
|
}
|
|
|
|
define internal void @__omp_outlined__19_wrapper(i16 zeroext %0, i32 %1) #0 {
|
|
entry:
|
|
%.addr = alloca i16, align 2
|
|
%.addr1 = alloca i32, align 4
|
|
%.zero.addr = alloca i32, align 4
|
|
%global_args = alloca ptr, align 8
|
|
store i32 0, ptr %.zero.addr, align 4
|
|
store i16 %0, ptr %.addr, align 2
|
|
store i32 %1, ptr %.addr1, align 4
|
|
call void @__kmpc_get_shared_variables(ptr %global_args)
|
|
call void @__omp_outlined__19(ptr %.addr1, ptr %.zero.addr) #3
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { convergent noinline norecurse nounwind "kernel" "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
attributes #1 = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
attributes #2 = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
attributes #3 = { nounwind }
|
|
attributes #4 = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
attributes #5 = { convergent nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
attributes #6 = { convergent nounwind }
|
|
attributes #7 = { convergent }
|
|
attributes #8 = { convergent "llvm.assume"="omp_no_openmp" }
|
|
attributes #9 = { convergent nounwind readonly willreturn }
|
|
|
|
!omp_offload.info = !{!0, !1, !2, !3, !4, !5, !6, !7}
|
|
!nvvm.annotations = !{!8, !9, !10, !11, !12, !13, !14, !15}
|
|
!llvm.module.flags = !{!16, !17, !18}
|
|
|
|
!0 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
|
|
!1 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
|
|
!2 = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
|
|
!3 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
|
|
!4 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
|
|
!5 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
|
|
!6 = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
|
|
!7 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
|
|
!8 = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
|
|
!9 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
|
|
!10 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
|
|
!11 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
|
|
!12 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
|
|
!13 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
|
|
!14 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
|
|
!15 = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
|
|
!16 = !{i32 1, !"wchar_size", i32 4}
|
|
!17 = !{i32 7, !"openmp", i32 50}
|
|
!18 = !{i32 7, !"openmp-device", i32 50}
|
|
;.
|
|
; AMDGPU: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
|
|
; AMDGPU: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; AMDGPU: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; AMDGPU: @[[G:[a-zA-Z0-9_$"\\.-]+]] = external global i32, align 4
|
|
; AMDGPU: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; AMDGPU: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_NEEDED_L14_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_L22_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_L39_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_WITH_FALLBACK_L55_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_NO_OPENMP_ATTR_L66_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_PURE_L77_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_NESTED_RECURSIVE_L92_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_WEAK_CALLEE_L112_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU: @[[__OMP_OUTLINED__2_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; AMDGPU: @[[__OMP_OUTLINED__3_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; AMDGPU: @[[__OMP_OUTLINED__5_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; AMDGPU: @[[__OMP_OUTLINED__7_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; AMDGPU: @[[__OMP_OUTLINED__8_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; AMDGPU: @[[__OMP_OUTLINED__10_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; AMDGPU: @[[__OMP_OUTLINED__11_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; AMDGPU: @[[__OMP_OUTLINED__13_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; AMDGPU: @[[__OMP_OUTLINED__14_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
;.
|
|
; NVPTX: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
|
|
; NVPTX: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; NVPTX: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; NVPTX: @[[G:[a-zA-Z0-9_$"\\.-]+]] = external global i32, align 4
|
|
; NVPTX: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; NVPTX: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_NEEDED_L14_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_L22_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_L39_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_WITH_FALLBACK_L55_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_NO_OPENMP_ATTR_L66_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_PURE_L77_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_NESTED_RECURSIVE_L92_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_WEAK_CALLEE_L112_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX: @[[__OMP_OUTLINED__2_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; NVPTX: @[[__OMP_OUTLINED__3_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; NVPTX: @[[__OMP_OUTLINED__5_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; NVPTX: @[[__OMP_OUTLINED__7_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; NVPTX: @[[__OMP_OUTLINED__8_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; NVPTX: @[[__OMP_OUTLINED__10_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; NVPTX: @[[__OMP_OUTLINED__11_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; NVPTX: @[[__OMP_OUTLINED__13_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
; NVPTX: @[[__OMP_OUTLINED__14_WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
|
|
;.
|
|
; AMDGPU-DISABLED: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
|
|
; AMDGPU-DISABLED: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; AMDGPU-DISABLED: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; AMDGPU-DISABLED: @[[G:[a-zA-Z0-9_$"\\.-]+]] = external global i32, align 4
|
|
; AMDGPU-DISABLED: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; AMDGPU-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_NEEDED_L14_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_L22_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_L39_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_WITH_FALLBACK_L55_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_NO_OPENMP_ATTR_L66_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_PURE_L77_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_NESTED_RECURSIVE_L92_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; AMDGPU-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_WEAK_CALLEE_L112_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
;.
|
|
; NVPTX-DISABLED: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
|
|
; NVPTX-DISABLED: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; NVPTX-DISABLED: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; NVPTX-DISABLED: @[[G:[a-zA-Z0-9_$"\\.-]+]] = external global i32, align 4
|
|
; NVPTX-DISABLED: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
|
|
; NVPTX-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_NEEDED_L14_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_L22_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_L39_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_WITH_FALLBACK_L55_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_NO_OPENMP_ATTR_L66_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_PURE_L77_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_NESTED_RECURSIVE_L92_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
; NVPTX-DISABLED: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_WEAK_CALLEE_L112_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null }
|
|
;.
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
|
|
; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU: user_code.entry:
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3:[0-9]+]]
|
|
; AMDGPU-NEXT: call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker.exit:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__kmpc_target_init
|
|
; AMDGPU-SAME: (ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) {
|
|
; AMDGPU-NEXT: ret i32 0
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9:[0-9]+]]
|
|
; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR10:[0-9]+]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
|
|
; AMDGPU-SAME: () #[[ATTR1:[0-9]+]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
; AMDGPU-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
|
|
; AMDGPU: omp_if.then:
|
|
; AMDGPU-NEXT: store i32 0, ptr @G, align 4
|
|
; AMDGPU-NEXT: call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: br label [[OMP_IF_END]]
|
|
; AMDGPU: omp_if.end:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@no_parallel_region_in_here
|
|
; AMDGPU-SAME: () #[[ATTR1]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
; AMDGPU-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
|
|
; AMDGPU: omp_if.then:
|
|
; AMDGPU-NEXT: store i32 0, ptr @G, align 4
|
|
; AMDGPU-NEXT: call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[OMP_IF_END]]
|
|
; AMDGPU: omp_if.end:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
|
|
; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; AMDGPU: is_worker_check:
|
|
; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; AMDGPU: worker_state_machine.begin:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; AMDGPU: worker_state_machine.finished:
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker_state_machine.is_active.check:
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check:
|
|
; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__2_wrapper.ID
|
|
; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__2_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check1:
|
|
; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute2:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check3:
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.end:
|
|
; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; AMDGPU: worker_state_machine.done.barrier:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; AMDGPU: thread.user_code.check:
|
|
; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU: user_code.entry:
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__omp_outlined__1(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker.exit:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__1
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__2
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p0() #[[ATTR11:[0-9]+]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__2(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__3
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p1() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__3(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
|
|
; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; AMDGPU: is_worker_check:
|
|
; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; AMDGPU: worker_state_machine.begin:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; AMDGPU: worker_state_machine.finished:
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker_state_machine.is_active.check:
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check:
|
|
; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__17_wrapper
|
|
; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__17_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check1:
|
|
; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION4:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__5_wrapper.ID
|
|
; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION4]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute2:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__5_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check3:
|
|
; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE5:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK6:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute5:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__18_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check6:
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.end:
|
|
; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; AMDGPU: worker_state_machine.done.barrier:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; AMDGPU: thread.user_code.check:
|
|
; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU: user_code.entry:
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__omp_outlined__4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker.exit:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__4
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]]
|
|
; AMDGPU-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
|
|
; AMDGPU-SAME: () #[[ATTR6:[0-9]+]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
|
|
; AMDGPU-SAME: () #[[ATTR1]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__5
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p1() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__5(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
|
|
; AMDGPU-SAME: () #[[ATTR6]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
|
|
; AMDGPU-SAME: () #[[ATTR1]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
|
|
; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; AMDGPU: is_worker_check:
|
|
; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; AMDGPU: worker_state_machine.begin:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; AMDGPU: worker_state_machine.finished:
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker_state_machine.is_active.check:
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check:
|
|
; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__7_wrapper.ID
|
|
; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__7_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check1:
|
|
; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION4:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__8_wrapper.ID
|
|
; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION4]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute2:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__8_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.fallback.execute:
|
|
; AMDGPU-NEXT: call void [[WORKER_WORK_FN_ADDR_CAST]](i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.end:
|
|
; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; AMDGPU: worker_state_machine.done.barrier:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; AMDGPU: thread.user_code.check:
|
|
; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU: user_code.entry:
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__omp_outlined__6(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker.exit:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__6
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]]
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__7
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__7(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__8
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p1() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__8(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
|
|
; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; AMDGPU: is_worker_check:
|
|
; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; AMDGPU: worker_state_machine.begin:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; AMDGPU: worker_state_machine.finished:
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker_state_machine.is_active.check:
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check:
|
|
; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__10_wrapper.ID
|
|
; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__10_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check1:
|
|
; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute2:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__11_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check3:
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.end:
|
|
; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; AMDGPU: worker_state_machine.done.barrier:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; AMDGPU: thread.user_code.check:
|
|
; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU: user_code.entry:
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__omp_outlined__9(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker.exit:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__9
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__10
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__10(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__11
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p1() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__11(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
|
|
; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; AMDGPU: is_worker_check:
|
|
; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; AMDGPU: worker_state_machine.begin:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; AMDGPU: worker_state_machine.finished:
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker_state_machine.is_active.check:
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check:
|
|
; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__13_wrapper.ID
|
|
; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__13_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check1:
|
|
; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.execute2:
|
|
; AMDGPU-NEXT: call void @__omp_outlined__14_wrapper(i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.check3:
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; AMDGPU: worker_state_machine.parallel_region.end:
|
|
; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; AMDGPU: worker_state_machine.done.barrier:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; AMDGPU: thread.user_code.check:
|
|
; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU: user_code.entry:
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__omp_outlined__12(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker.exit:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__12
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__13
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__13(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__14
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p1() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__14(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
|
|
; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU: user_code.entry:
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__omp_outlined__15(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker.exit:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__15
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[CALL:%.*]] = call i32 @omp_get_thread_num() #[[ATTR9]]
|
|
; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[CALL]]) #[[ATTR9]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized
|
|
; AMDGPU-SAME: (i32 [[A:%.*]]) #[[ATTR6]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; AMDGPU-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
|
|
; AMDGPU-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
|
; AMDGPU: if.then:
|
|
; AMDGPU-NEXT: br label [[RETURN:%.*]]
|
|
; AMDGPU: if.end:
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; AMDGPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
|
|
; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR9]]
|
|
; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR9]]
|
|
; AMDGPU-NEXT: br label [[RETURN]]
|
|
; AMDGPU: return:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
|
|
; AMDGPU-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; AMDGPU-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
|
|
; AMDGPU-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
|
; AMDGPU: if.then:
|
|
; AMDGPU-NEXT: br label [[RETURN:%.*]]
|
|
; AMDGPU: if.end:
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; AMDGPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
|
|
; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]]) #[[ATTR11]]
|
|
; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[[ATTR11]]
|
|
; AMDGPU-NEXT: br label [[RETURN]]
|
|
; AMDGPU: return:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
|
|
; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; AMDGPU: is_worker_check:
|
|
; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; AMDGPU: worker_state_machine.begin:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]])
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
|
|
; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; AMDGPU: worker_state_machine.finished:
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker_state_machine.is_active.check:
|
|
; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.fallback.execute:
|
|
; AMDGPU-NEXT: call void [[WORKER_WORK_FN_ADDR_CAST]](i16 0, i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; AMDGPU: worker_state_machine.parallel_region.end:
|
|
; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; AMDGPU: worker_state_machine.done.barrier:
|
|
; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; AMDGPU: thread.user_code.check:
|
|
; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU: user_code.entry:
|
|
; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__omp_outlined__16(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-NEXT: ret void
|
|
; AMDGPU: worker.exit:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__16
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @weak_callee_empty() #[[ATTR9]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@weak_callee_empty
|
|
; AMDGPU-SAME: () #[[ATTR1]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__17
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__17(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__18
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__18(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
|
|
; AMDGPU-SAME: () #[[ATTR6]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
|
|
; AMDGPU-SAME: () #[[ATTR1]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__19
|
|
; AMDGPU-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
|
|
; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-NEXT: entry:
|
|
; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-NEXT: call void @__omp_outlined__19(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
|
|
; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX: user_code.entry:
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3:[0-9]+]]
|
|
; NVPTX-NEXT: call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker.exit:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-LABEL: define {{[^@]+}}@__kmpc_target_init
|
|
; NVPTX-SAME: (ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) {
|
|
; NVPTX-NEXT: ret i32 0
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9:[0-9]+]]
|
|
; NVPTX-NEXT: call void @unknown_no_openmp() #[[ATTR10:[0-9]+]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
|
|
; NVPTX-SAME: () #[[ATTR1:[0-9]+]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
; NVPTX-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
|
|
; NVPTX: omp_if.then:
|
|
; NVPTX-NEXT: store i32 0, ptr @G, align 4
|
|
; NVPTX-NEXT: call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: br label [[OMP_IF_END]]
|
|
; NVPTX: omp_if.end:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@no_parallel_region_in_here
|
|
; NVPTX-SAME: () #[[ATTR1]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
; NVPTX-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
|
|
; NVPTX: omp_if.then:
|
|
; NVPTX-NEXT: store i32 0, ptr @G, align 4
|
|
; NVPTX-NEXT: call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[OMP_IF_END]]
|
|
; NVPTX: omp_if.end:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
|
|
; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; NVPTX: is_worker_check:
|
|
; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; NVPTX: worker_state_machine.begin:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]])
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; NVPTX: worker_state_machine.finished:
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker_state_machine.is_active.check:
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.check:
|
|
; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__2_wrapper.ID
|
|
; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute:
|
|
; NVPTX-NEXT: call void @__omp_outlined__2_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.check1:
|
|
; NVPTX-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute2:
|
|
; NVPTX-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.check3:
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.end:
|
|
; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; NVPTX: worker_state_machine.done.barrier:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; NVPTX: thread.user_code.check:
|
|
; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX: user_code.entry:
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__omp_outlined__1(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker.exit:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__1
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__2
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p0() #[[ATTR11:[0-9]+]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__2(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__3
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p1() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__3(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
|
|
; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; NVPTX: is_worker_check:
|
|
; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; NVPTX: worker_state_machine.begin:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]])
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; NVPTX: worker_state_machine.finished:
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker_state_machine.is_active.check:
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.check:
|
|
; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__17_wrapper
|
|
; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute:
|
|
; NVPTX-NEXT: call void @__omp_outlined__17_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.check1:
|
|
; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION4:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__5_wrapper.ID
|
|
; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION4]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute2:
|
|
; NVPTX-NEXT: call void @__omp_outlined__5_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.check3:
|
|
; NVPTX-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE5:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK6:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute5:
|
|
; NVPTX-NEXT: call void @__omp_outlined__18_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.check6:
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.end:
|
|
; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; NVPTX: worker_state_machine.done.barrier:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; NVPTX: thread.user_code.check:
|
|
; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX: user_code.entry:
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__omp_outlined__4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker.exit:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__4
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; NVPTX-NEXT: call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]]
|
|
; NVPTX-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
|
|
; NVPTX-SAME: () #[[ATTR6:[0-9]+]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
|
|
; NVPTX-SAME: () #[[ATTR1]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__5
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p1() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__5(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
|
|
; NVPTX-SAME: () #[[ATTR6]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
|
|
; NVPTX-SAME: () #[[ATTR1]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
|
|
; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; NVPTX: is_worker_check:
|
|
; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; NVPTX: worker_state_machine.begin:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]])
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; NVPTX: worker_state_machine.finished:
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker_state_machine.is_active.check:
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.check:
|
|
; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__7_wrapper.ID
|
|
; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute:
|
|
; NVPTX-NEXT: call void @__omp_outlined__7_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.check1:
|
|
; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION4:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__8_wrapper.ID
|
|
; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION4]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute2:
|
|
; NVPTX-NEXT: call void @__omp_outlined__8_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.fallback.execute:
|
|
; NVPTX-NEXT: call void [[WORKER_WORK_FN_ADDR_CAST]](i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.end:
|
|
; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; NVPTX: worker_state_machine.done.barrier:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; NVPTX: thread.user_code.check:
|
|
; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX: user_code.entry:
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__omp_outlined__6(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker.exit:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__6
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]]
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__7
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__7(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__8
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p1() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__8(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
|
|
; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; NVPTX: is_worker_check:
|
|
; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; NVPTX: worker_state_machine.begin:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]])
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; NVPTX: worker_state_machine.finished:
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker_state_machine.is_active.check:
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.check:
|
|
; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__10_wrapper.ID
|
|
; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute:
|
|
; NVPTX-NEXT: call void @__omp_outlined__10_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.check1:
|
|
; NVPTX-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute2:
|
|
; NVPTX-NEXT: call void @__omp_outlined__11_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.check3:
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.end:
|
|
; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; NVPTX: worker_state_machine.done.barrier:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; NVPTX: thread.user_code.check:
|
|
; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX: user_code.entry:
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__omp_outlined__9(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker.exit:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__9
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__10
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__10(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__11
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p1() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__11(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
|
|
; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; NVPTX: is_worker_check:
|
|
; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; NVPTX: worker_state_machine.begin:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]])
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; NVPTX: worker_state_machine.finished:
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker_state_machine.is_active.check:
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.check:
|
|
; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN_ADDR_CAST]], @__omp_outlined__13_wrapper.ID
|
|
; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute:
|
|
; NVPTX-NEXT: call void @__omp_outlined__13_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.check1:
|
|
; NVPTX-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.execute2:
|
|
; NVPTX-NEXT: call void @__omp_outlined__14_wrapper(i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.check3:
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
|
|
; NVPTX: worker_state_machine.parallel_region.end:
|
|
; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; NVPTX: worker_state_machine.done.barrier:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; NVPTX: thread.user_code.check:
|
|
; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX: user_code.entry:
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__omp_outlined__12(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker.exit:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__12
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__13
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__13(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__14
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p1() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__14(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
|
|
; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX: user_code.entry:
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__omp_outlined__15(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker.exit:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__15
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[CALL:%.*]] = call i32 @omp_get_thread_num() #[[ATTR9]]
|
|
; NVPTX-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[CALL]]) #[[ATTR9]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized
|
|
; NVPTX-SAME: (i32 [[A:%.*]]) #[[ATTR6]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; NVPTX-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
|
|
; NVPTX-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
|
; NVPTX: if.then:
|
|
; NVPTX-NEXT: br label [[RETURN:%.*]]
|
|
; NVPTX: if.end:
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; NVPTX-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
|
|
; NVPTX-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR9]]
|
|
; NVPTX-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR9]]
|
|
; NVPTX-NEXT: br label [[RETURN]]
|
|
; NVPTX: return:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
|
|
; NVPTX-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; NVPTX-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
|
|
; NVPTX-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
|
; NVPTX: if.then:
|
|
; NVPTX-NEXT: br label [[RETURN:%.*]]
|
|
; NVPTX: if.end:
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; NVPTX-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
|
|
; NVPTX-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]]) #[[ATTR11]]
|
|
; NVPTX-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[[ATTR11]]
|
|
; NVPTX-NEXT: br label [[RETURN]]
|
|
; NVPTX: return:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
|
|
; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]]
|
|
; NVPTX: is_worker_check:
|
|
; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
|
; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
|
|
; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
|
|
; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
|
|
; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]]
|
|
; NVPTX: worker_state_machine.begin:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]])
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8
|
|
; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast ptr [[WORKER_WORK_FN]] to ptr
|
|
; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
|
|
; NVPTX: worker_state_machine.finished:
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker_state_machine.is_active.check:
|
|
; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.fallback.execute:
|
|
; NVPTX-NEXT: call void [[WORKER_WORK_FN_ADDR_CAST]](i16 0, i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
|
|
; NVPTX: worker_state_machine.parallel_region.end:
|
|
; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel()
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
|
|
; NVPTX: worker_state_machine.done.barrier:
|
|
; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]])
|
|
; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
|
|
; NVPTX: thread.user_code.check:
|
|
; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX: user_code.entry:
|
|
; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__omp_outlined__16(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-NEXT: ret void
|
|
; NVPTX: worker.exit:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__16
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @weak_callee_empty() #[[ATTR9]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@weak_callee_empty
|
|
; NVPTX-SAME: () #[[ATTR1]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__17
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__17(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__18
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__18(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
|
|
; NVPTX-SAME: () #[[ATTR6]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
|
|
; NVPTX-SAME: () #[[ATTR1]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__19
|
|
; NVPTX-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
|
|
; NVPTX-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-NEXT: entry:
|
|
; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-NEXT: call void @__omp_outlined__19(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
|
|
; AMDGPU-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU-DISABLED: user_code.entry:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3:[0-9]+]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
; AMDGPU-DISABLED: worker.exit:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__kmpc_target_init
|
|
; AMDGPU-DISABLED-SAME: (ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) {
|
|
; AMDGPU-DISABLED-NEXT: ret i32 0
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9:[0-9]+]]
|
|
; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR10:[0-9]+]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
|
|
; AMDGPU-DISABLED-SAME: () #[[ATTR1:[0-9]+]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
|
|
; AMDGPU-DISABLED: omp_if.then:
|
|
; AMDGPU-DISABLED-NEXT: store i32 0, ptr @G, align 4
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: br label [[OMP_IF_END]]
|
|
; AMDGPU-DISABLED: omp_if.end:
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@no_parallel_region_in_here
|
|
; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]])
|
|
; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
|
|
; AMDGPU-DISABLED: omp_if.then:
|
|
; AMDGPU-DISABLED-NEXT: store i32 0, ptr @G, align 4
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]])
|
|
; AMDGPU-DISABLED-NEXT: br label [[OMP_IF_END]]
|
|
; AMDGPU-DISABLED: omp_if.end:
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
|
|
; AMDGPU-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU-DISABLED: user_code.entry:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__1(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
; AMDGPU-DISABLED: worker.exit:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__1
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR11:[0-9]+]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__2(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__3(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
|
|
; AMDGPU-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU-DISABLED: user_code.entry:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
; AMDGPU-DISABLED: worker.exit:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__4
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]]
|
|
; AMDGPU-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
|
|
; AMDGPU-DISABLED-SAME: () #[[ATTR6:[0-9]+]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
|
|
; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__5(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
|
|
; AMDGPU-DISABLED-SAME: () #[[ATTR6]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
|
|
; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
|
|
; AMDGPU-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU-DISABLED: user_code.entry:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__6(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
; AMDGPU-DISABLED: worker.exit:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__6
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__7(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__8(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
|
|
; AMDGPU-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU-DISABLED: user_code.entry:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__9(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
; AMDGPU-DISABLED: worker.exit:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__9
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__10(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__11(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
|
|
; AMDGPU-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU-DISABLED: user_code.entry:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__12(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
; AMDGPU-DISABLED: worker.exit:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__12
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__13(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__14(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
|
|
; AMDGPU-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU-DISABLED: user_code.entry:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__15(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
; AMDGPU-DISABLED: worker.exit:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__15
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[CALL:%.*]] = call i32 @omp_get_thread_num() #[[ATTR9]]
|
|
; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[CALL]]) #[[ATTR9]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized
|
|
; AMDGPU-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR6]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; AMDGPU-DISABLED-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
|
; AMDGPU-DISABLED: if.then:
|
|
; AMDGPU-DISABLED-NEXT: br label [[RETURN:%.*]]
|
|
; AMDGPU-DISABLED: if.end:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; AMDGPU-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
|
|
; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR9]]
|
|
; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR9]]
|
|
; AMDGPU-DISABLED-NEXT: br label [[RETURN]]
|
|
; AMDGPU-DISABLED: return:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
|
|
; AMDGPU-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; AMDGPU-DISABLED-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
|
; AMDGPU-DISABLED: if.then:
|
|
; AMDGPU-DISABLED-NEXT: br label [[RETURN:%.*]]
|
|
; AMDGPU-DISABLED: if.end:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; AMDGPU-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
|
|
; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]]) #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: br label [[RETURN]]
|
|
; AMDGPU-DISABLED: return:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
|
|
; AMDGPU-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment, ptr [[DYN]])
|
|
; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; AMDGPU-DISABLED: user_code.entry:
|
|
; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__16(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
; AMDGPU-DISABLED: worker.exit:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__16
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @weak_callee_empty() #[[ATTR9]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@weak_callee_empty
|
|
; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__17(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__18(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
|
|
; AMDGPU-DISABLED-SAME: () #[[ATTR6]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
|
|
; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19
|
|
; AMDGPU-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
|
|
; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; AMDGPU-DISABLED-NEXT: entry:
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__19(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; AMDGPU-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
|
|
; NVPTX-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX-DISABLED: user_code.entry:
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3:[0-9]+]]
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
; NVPTX-DISABLED: worker.exit:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__kmpc_target_init
|
|
; NVPTX-DISABLED-SAME: (ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) {
|
|
; NVPTX-DISABLED-NEXT: ret i32 0
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9:[0-9]+]]
|
|
; NVPTX-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR10:[0-9]+]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
|
|
; NVPTX-DISABLED-SAME: () #[[ATTR1:[0-9]+]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
; NVPTX-DISABLED-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
|
|
; NVPTX-DISABLED: omp_if.then:
|
|
; NVPTX-DISABLED-NEXT: store i32 0, ptr @G, align 4
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: br label [[OMP_IF_END]]
|
|
; NVPTX-DISABLED: omp_if.end:
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@no_parallel_region_in_here
|
|
; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]])
|
|
; NVPTX-DISABLED-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
; NVPTX-DISABLED-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
|
|
; NVPTX-DISABLED: omp_if.then:
|
|
; NVPTX-DISABLED-NEXT: store i32 0, ptr @G, align 4
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]])
|
|
; NVPTX-DISABLED-NEXT: br label [[OMP_IF_END]]
|
|
; NVPTX-DISABLED: omp_if.end:
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
|
|
; NVPTX-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX-DISABLED: user_code.entry:
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__1(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
; NVPTX-DISABLED: worker.exit:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__1
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR11:[0-9]+]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__2(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__3(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
|
|
; NVPTX-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX-DISABLED: user_code.entry:
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
; NVPTX-DISABLED: worker.exit:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__4
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]]
|
|
; NVPTX-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
|
|
; NVPTX-DISABLED-SAME: () #[[ATTR6:[0-9]+]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
|
|
; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__5(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
|
|
; NVPTX-DISABLED-SAME: () #[[ATTR6]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
|
|
; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
|
|
; NVPTX-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX-DISABLED: user_code.entry:
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__6(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
; NVPTX-DISABLED: worker.exit:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__6
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__7(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__8(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
|
|
; NVPTX-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX-DISABLED: user_code.entry:
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__9(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
; NVPTX-DISABLED: worker.exit:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__9
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__10(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__11(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
|
|
; NVPTX-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX-DISABLED: user_code.entry:
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__12(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
; NVPTX-DISABLED: worker.exit:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__12
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR10]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__13(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__14(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
|
|
; NVPTX-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX-DISABLED: user_code.entry:
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__15(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
; NVPTX-DISABLED: worker.exit:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__15
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[CALL:%.*]] = call i32 @omp_get_thread_num() #[[ATTR9]]
|
|
; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[CALL]]) #[[ATTR9]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized
|
|
; NVPTX-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR6]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; NVPTX-DISABLED-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
|
|
; NVPTX-DISABLED-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
|
; NVPTX-DISABLED: if.then:
|
|
; NVPTX-DISABLED-NEXT: br label [[RETURN:%.*]]
|
|
; NVPTX-DISABLED: if.end:
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; NVPTX-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
|
|
; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR9]]
|
|
; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR9]]
|
|
; NVPTX-DISABLED-NEXT: br label [[RETURN]]
|
|
; NVPTX-DISABLED: return:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
|
|
; NVPTX-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; NVPTX-DISABLED-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
|
|
; NVPTX-DISABLED-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
|
; NVPTX-DISABLED: if.then:
|
|
; NVPTX-DISABLED-NEXT: br label [[RETURN:%.*]]
|
|
; NVPTX-DISABLED: if.end:
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
; NVPTX-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
|
|
; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]]) #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: br label [[RETURN]]
|
|
; NVPTX-DISABLED: return:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
|
|
; NVPTX-DISABLED-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment, ptr [[DYN]])
|
|
; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
|
; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
; NVPTX-DISABLED: user_code.entry:
|
|
; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__16(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit()
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
; NVPTX-DISABLED: worker.exit:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__16
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @weak_callee_empty() #[[ATTR9]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@weak_callee_empty
|
|
; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__17(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__18(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
|
|
; NVPTX-DISABLED-SAME: () #[[ATTR6]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
|
|
; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
|
; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19
|
|
; NVPTX-DISABLED-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR11]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;
|
|
; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
|
|
; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
|
|
; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
|
|
; NVPTX-DISABLED-NEXT: entry:
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
|
|
; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
|
; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
|
|
; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
|
|
; NVPTX-DISABLED-NEXT: call void @__omp_outlined__19(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
|
|
; NVPTX-DISABLED-NEXT: ret void
|
|
;
|
|
;.
|
|
; AMDGPU: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU: attributes #[[ATTR1]] = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU: attributes #[[ATTR2:[0-9]+]] = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU: attributes #[[ATTR3]] = { nounwind }
|
|
; AMDGPU: attributes #[[ATTR4:[0-9]+]] = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU: attributes #[[ATTR5:[0-9]+]] = { alwaysinline }
|
|
; AMDGPU: attributes #[[ATTR6]] = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU: attributes #[[ATTR7:[0-9]+]] = { convergent nounwind willreturn memory(read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU: attributes #[[ATTR9]] = { convergent nounwind }
|
|
; AMDGPU: attributes #[[ATTR10]] = { convergent "llvm.assume"="omp_no_openmp" }
|
|
; AMDGPU: attributes #[[ATTR11]] = { convergent }
|
|
;.
|
|
; NVPTX: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX: attributes #[[ATTR1]] = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX: attributes #[[ATTR2:[0-9]+]] = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX: attributes #[[ATTR3]] = { nounwind }
|
|
; NVPTX: attributes #[[ATTR4:[0-9]+]] = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX: attributes #[[ATTR5:[0-9]+]] = { alwaysinline }
|
|
; NVPTX: attributes #[[ATTR6]] = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX: attributes #[[ATTR7:[0-9]+]] = { convergent nounwind willreturn memory(read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX: attributes #[[ATTR9]] = { convergent nounwind }
|
|
; NVPTX: attributes #[[ATTR10]] = { convergent "llvm.assume"="omp_no_openmp" }
|
|
; NVPTX: attributes #[[ATTR11]] = { convergent }
|
|
;.
|
|
; AMDGPU-DISABLED: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR1]] = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR2:[0-9]+]] = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR3]] = { nounwind }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR4:[0-9]+]] = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR5:[0-9]+]] = { alwaysinline }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR6]] = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR7:[0-9]+]] = { convergent nounwind willreturn memory(read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR9]] = { convergent nounwind }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR10]] = { convergent "llvm.assume"="omp_no_openmp" }
|
|
; AMDGPU-DISABLED: attributes #[[ATTR11]] = { convergent }
|
|
;.
|
|
; NVPTX-DISABLED: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX-DISABLED: attributes #[[ATTR1]] = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX-DISABLED: attributes #[[ATTR2:[0-9]+]] = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX-DISABLED: attributes #[[ATTR3]] = { nounwind }
|
|
; NVPTX-DISABLED: attributes #[[ATTR4:[0-9]+]] = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX-DISABLED: attributes #[[ATTR5:[0-9]+]] = { alwaysinline }
|
|
; NVPTX-DISABLED: attributes #[[ATTR6]] = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX-DISABLED: attributes #[[ATTR7:[0-9]+]] = { convergent nounwind willreturn memory(read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX-DISABLED: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
|
|
; NVPTX-DISABLED: attributes #[[ATTR9]] = { convergent nounwind }
|
|
; NVPTX-DISABLED: attributes #[[ATTR10]] = { convergent "llvm.assume"="omp_no_openmp" }
|
|
; NVPTX-DISABLED: attributes #[[ATTR11]] = { convergent }
|
|
;.
|
|
; AMDGPU: [[META0:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
|
|
; AMDGPU: [[META1:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
|
|
; AMDGPU: [[META2:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
|
|
; AMDGPU: [[META3:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
|
|
; AMDGPU: [[META4:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
|
|
; AMDGPU: [[META5:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
|
|
; AMDGPU: [[META6:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
|
|
; AMDGPU: [[META7:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
|
|
; AMDGPU: [[META8:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
|
|
; AMDGPU: [[META9:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
|
|
; AMDGPU: [[META10:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
|
|
; AMDGPU: [[META11:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
|
|
; AMDGPU: [[META12:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
|
|
; AMDGPU: [[META13:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
|
|
; AMDGPU: [[META14:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
|
|
; AMDGPU: [[META15:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
|
|
; AMDGPU: [[META16:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
|
|
; AMDGPU: [[META17:![0-9]+]] = !{i32 7, !"openmp", i32 50}
|
|
; AMDGPU: [[META18:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
|
|
;.
|
|
; NVPTX: [[META0:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
|
|
; NVPTX: [[META1:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
|
|
; NVPTX: [[META2:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
|
|
; NVPTX: [[META3:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
|
|
; NVPTX: [[META4:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
|
|
; NVPTX: [[META5:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
|
|
; NVPTX: [[META6:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
|
|
; NVPTX: [[META7:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
|
|
; NVPTX: [[META8:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
|
|
; NVPTX: [[META9:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
|
|
; NVPTX: [[META10:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
|
|
; NVPTX: [[META11:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
|
|
; NVPTX: [[META12:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
|
|
; NVPTX: [[META13:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
|
|
; NVPTX: [[META14:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
|
|
; NVPTX: [[META15:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
|
|
; NVPTX: [[META16:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
|
|
; NVPTX: [[META17:![0-9]+]] = !{i32 7, !"openmp", i32 50}
|
|
; NVPTX: [[META18:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
|
|
;.
|
|
; AMDGPU-DISABLED: [[META0:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
|
|
; AMDGPU-DISABLED: [[META1:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
|
|
; AMDGPU-DISABLED: [[META2:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
|
|
; AMDGPU-DISABLED: [[META3:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
|
|
; AMDGPU-DISABLED: [[META4:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
|
|
; AMDGPU-DISABLED: [[META5:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
|
|
; AMDGPU-DISABLED: [[META6:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
|
|
; AMDGPU-DISABLED: [[META7:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
|
|
; AMDGPU-DISABLED: [[META8:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
|
|
; AMDGPU-DISABLED: [[META9:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
|
|
; AMDGPU-DISABLED: [[META10:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
|
|
; AMDGPU-DISABLED: [[META11:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
|
|
; AMDGPU-DISABLED: [[META12:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
|
|
; AMDGPU-DISABLED: [[META13:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
|
|
; AMDGPU-DISABLED: [[META14:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
|
|
; AMDGPU-DISABLED: [[META15:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
|
|
; AMDGPU-DISABLED: [[META16:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
|
|
; AMDGPU-DISABLED: [[META17:![0-9]+]] = !{i32 7, !"openmp", i32 50}
|
|
; AMDGPU-DISABLED: [[META18:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
|
|
;.
|
|
; NVPTX-DISABLED: [[META0:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
|
|
; NVPTX-DISABLED: [[META1:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
|
|
; NVPTX-DISABLED: [[META2:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
|
|
; NVPTX-DISABLED: [[META3:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
|
|
; NVPTX-DISABLED: [[META4:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
|
|
; NVPTX-DISABLED: [[META5:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
|
|
; NVPTX-DISABLED: [[META6:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
|
|
; NVPTX-DISABLED: [[META7:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
|
|
; NVPTX-DISABLED: [[META8:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
|
|
; NVPTX-DISABLED: [[META9:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
|
|
; NVPTX-DISABLED: [[META10:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
|
|
; NVPTX-DISABLED: [[META11:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
|
|
; NVPTX-DISABLED: [[META12:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
|
|
; NVPTX-DISABLED: [[META13:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
|
|
; NVPTX-DISABLED: [[META14:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
|
|
; NVPTX-DISABLED: [[META15:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
|
|
; NVPTX-DISABLED: [[META16:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
|
|
; NVPTX-DISABLED: [[META17:![0-9]+]] = !{i32 7, !"openmp", i32 50}
|
|
; NVPTX-DISABLED: [[META18:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
|
|
;.
|