a789f40002
Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
14 lines
297 B
LLVM
14 lines
297 B
LLVM
; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
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; Checks that atomic fences are simply removed from IR.
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; AVR is always singlethreaded so fences do nothing.
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; CHECK_LABEL: atomic_fence8
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; CHECK: ; BB#0:
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; CHECK-NEXT: ret
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define void @atomic_fence8() {
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fence acquire
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ret void
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}
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