a789f40002
Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
138 lines
4.0 KiB
LLVM
138 lines
4.0 KiB
LLVM
; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
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; CHECK-LABEL: atomic_load16
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
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; CHECK-NEXT: ldd [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]+
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; CHECK-NEXT: out 63, r0
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define i16 @atomic_load16(i16* %foo) {
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%val = load atomic i16, i16* %foo unordered, align 2
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_swap16
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; CHECK: call __sync_lock_test_and_set_2
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define i16 @atomic_load_swap16(i16* %foo) {
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%val = atomicrmw xchg i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_cmp_swap16
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; CHECK: call __sync_val_compare_and_swap_2
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define i16 @atomic_load_cmp_swap16(i16* %foo) {
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%val = cmpxchg i16* %foo, i16 5, i16 10 acq_rel monotonic
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%value_loaded = extractvalue { i16, i1 } %val, 0
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ret i16 %value_loaded
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}
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; CHECK-LABEL: atomic_load_add16
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
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; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
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; CHECK-NEXT: add [[RR1]], [[TMP:r[0-9]+]]
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; CHECK-NEXT: adc [[RR2]], [[TMP:r[0-9]+]]
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; CHECK-NEXT: st [[RD1]], [[RR1]]
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; CHECK-NEXT: std [[RD1]]+1, [[A:r[0-9]+]]
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; CHECK-NEXT: out 63, r0
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define i16 @atomic_load_add16(i16* %foo) {
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%val = atomicrmw add i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_sub16
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
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; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
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; CHECK-NEXT: sub [[RR1]], [[TMP:r[0-9]+]]
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; CHECK-NEXT: sbc [[RR2]], [[TMP:r[0-9]+]]
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; CHECK-NEXT: st [[RD1]], [[RR1]]
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; CHECK-NEXT: std [[RD1]]+1, [[A:r[0-9]+]]
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; CHECK-NEXT: out 63, r0
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define i16 @atomic_load_sub16(i16* %foo) {
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%val = atomicrmw sub i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_and16
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
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; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
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; CHECK-NEXT: and [[RR1]], [[TMP:r[0-9]+]]
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; CHECK-NEXT: and [[RR2]], [[TMP:r[0-9]+]]
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; CHECK-NEXT: st [[RD1]], [[RR1]]
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; CHECK-NEXT: std [[RD1]]+1, [[A:r[0-9]+]]
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; CHECK-NEXT: out 63, r0
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define i16 @atomic_load_and16(i16* %foo) {
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%val = atomicrmw and i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_or16
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
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; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
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; CHECK-NEXT: or [[RR1]], [[TMP:r[0-9]+]]
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; CHECK-NEXT: or [[RR2]], [[TMP:r[0-9]+]]
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; CHECK-NEXT: st [[RD1]], [[RR1]]
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; CHECK-NEXT: std [[RD1]]+1, [[A:r[0-9]+]]
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; CHECK-NEXT: out 63, r0
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define i16 @atomic_load_or16(i16* %foo) {
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%val = atomicrmw or i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_xor16
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
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; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
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; CHECK-NEXT: eor [[RR1]], [[TMP:r[0-9]+]]
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; CHECK-NEXT: eor [[RR2]], [[TMP:r[0-9]+]]
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; CHECK-NEXT: st [[RD1]], [[RR1]]
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; CHECK-NEXT: std [[RD1]]+1, [[A:r[0-9]+]]
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; CHECK-NEXT: out 63, r0
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define i16 @atomic_load_xor16(i16* %foo) {
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%val = atomicrmw xor i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_nand16
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; CHECK: call __sync_fetch_and_nand_2
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define i16 @atomic_load_nand16(i16* %foo) {
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%val = atomicrmw nand i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_max16
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; CHECK: call __sync_fetch_and_max_2
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define i16 @atomic_load_max16(i16* %foo) {
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%val = atomicrmw max i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_min16
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; CHECK: call __sync_fetch_and_min_2
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define i16 @atomic_load_min16(i16* %foo) {
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%val = atomicrmw min i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_umax16
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; CHECK: call __sync_fetch_and_umax_2
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define i16 @atomic_load_umax16(i16* %foo) {
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%val = atomicrmw umax i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_load_umin16
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; CHECK: call __sync_fetch_and_umin_2
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define i16 @atomic_load_umin16(i16* %foo) {
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%val = atomicrmw umin i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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