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clang-p2996/llvm/test/CodeGen/MIR/AMDGPU
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Marek Olsak 79c05871a2 AMDGPU/SI: Add back reverted SGPR spilling code, but disable it 
suggested as a better solution by Matt

llvm-svn: 287942
2016-11-25 17:37:09 +00:00
..
expected-target-index-name.mir
MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it
2016-08-24 22:17:45 +00:00
inserted-wait-states.mir
AMDGPU/SI: Handle hazard with s_rfe_b64
2016-10-27 23:50:21 +00:00
intrinsics.mir
GlobalISel: move type information to MachineRegisterInfo.
2016-09-09 11:46:34 +00:00
invalid-target-index-operand.mir
MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it
2016-08-24 22:17:45 +00:00
invert-br-undef-vcc.mir
AMDGPU: Preserve vcc undef flags when inverting branch
2016-11-07 19:09:27 +00:00
lit.local.cfg
…
movrels-bug.mir
AMDGPU: Allow additional implicit operands on MOVRELS instructions
2016-11-02 17:03:11 +00:00
optimize-if-exec-masking.mir
AMDGPU: Partially fix control flow at -O0
2016-09-29 01:44:16 +00:00
scalar-store-cache-flush.mir
AMDGPU/SI: Add back reverted SGPR spilling code, but disable it
2016-11-25 17:37:09 +00:00
si-fix-sgpr-copies.mir
AMDGPU/SI: Add back reverted SGPR spilling code, but disable it
2016-11-25 17:37:09 +00:00
target-index-operands.mir
AMDGPU: Add definitions for scalar store instructions
2016-10-28 21:55:15 +00:00
vccz-corrupt-bug-workaround.mir
AMDGPU: Preserve vcc undef flags when inverting branch
2016-11-07 19:09:27 +00:00
waitcnt.mir
AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructions
2016-10-28 23:53:48 +00:00