c62266d680
When we predicate an instruction (div, rem, store) we place the instruction in its own basic block within the vectorized loop. If a predicated instruction has scalar operands, it's possible to recursively sink these scalar expressions into the predicated block so that they might avoid execution. This patch sinks as much scalar computation as possible into predicated blocks. We previously were able to sink such operands only if they were extractelement instructions. Differential Revision: https://reviews.llvm.org/D25632 llvm-svn: 285097
133 lines
5.0 KiB
LLVM
133 lines
5.0 KiB
LLVM
; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=UNROLL
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; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info < %s | FileCheck %s --check-prefix=UNROLL-NOSIMPLIFY
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; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -enable-cond-stores-vec -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=VEC
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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; Test predication of stores.
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define i32 @test(i32* nocapture %f) #0 {
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entry:
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br label %for.body
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; VEC-LABEL: test
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; VEC: %[[v0:.+]] = add i64 %index, 0
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; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100>
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; VEC: %[[v9:.+]] = add nsw <2 x i32> %{{.*}}, <i32 20, i32 20>
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; VEC: %[[v10:.+]] = and <2 x i1> %[[v8]], <i1 true, i1 true>
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; VEC: %[[o1:.+]] = or <2 x i1> zeroinitializer, %[[v10]]
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; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[o1]], i32 0
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; VEC: %[[v12:.+]] = icmp eq i1 %[[v11]], true
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; VEC: br i1 %[[v12]], label %[[cond:.+]], label %[[else:.+]]
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;
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; VEC: [[cond]]:
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; VEC: %[[v13:.+]] = extractelement <2 x i32> %[[v9]], i32 0
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; VEC: %[[v2:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v0]]
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; VEC: store i32 %[[v13]], i32* %[[v2]], align 4
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; VEC: br label %[[else:.+]]
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;
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; VEC: [[else]]:
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; VEC: %[[v15:.+]] = extractelement <2 x i1> %[[o1]], i32 1
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; VEC: %[[v16:.+]] = icmp eq i1 %[[v15]], true
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; VEC: br i1 %[[v16]], label %[[cond2:.+]], label %[[else2:.+]]
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;
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; VEC: [[cond2]]:
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; VEC: %[[v17:.+]] = extractelement <2 x i32> %[[v9]], i32 1
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; VEC: %[[v1:.+]] = add i64 %index, 1
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; VEC: %[[v4:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v1]]
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; VEC: store i32 %[[v17]], i32* %[[v4]], align 4
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; VEC: br label %[[else2:.+]]
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;
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; VEC: [[else2]]:
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; UNROLL-LABEL: test
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; UNROLL: vector.body:
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; UNROLL: %[[IND:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 0
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; UNROLL: %[[IND1:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 1
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; UNROLL: %[[v0:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND]]
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; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]]
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; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4
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; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4
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; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100
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; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100
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; UNROLL: %[[o1:[a-zA-Z0-9]+]] = or i1 false, %[[v4]]
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; UNROLL: %[[o2:[a-zA-Z0-9]+]] = or i1 false, %[[v5]]
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; UNROLL: %[[v8:[a-zA-Z0-9]+]] = icmp eq i1 %[[o1]], true
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; UNROLL: br i1 %[[v8]], label %[[cond:[a-zA-Z0-9.]+]], label %[[else:[a-zA-Z0-9.]+]]
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;
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; UNROLL: [[cond]]:
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; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20
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; UNROLL: store i32 %[[v6]], i32* %[[v0]], align 4
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; UNROLL: br label %[[else]]
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;
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; UNROLL: [[else]]:
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; UNROLL: %[[v9:[a-zA-Z0-9]+]] = icmp eq i1 %[[o2]], true
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; UNROLL: br i1 %[[v9]], label %[[cond2:[a-zA-Z0-9.]+]], label %[[else2:[a-zA-Z0-9.]+]]
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;
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; UNROLL: [[cond2]]:
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; UNROLL: %[[v7:[a-zA-Z0-9]+]] = add nsw i32 %[[v3]], 20
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; UNROLL: store i32 %[[v7]], i32* %[[v1]], align 4
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; UNROLL: br label %[[else2]]
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;
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; UNROLL: [[else2]]:
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
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%arrayidx = getelementptr inbounds i32, i32* %f, i64 %indvars.iv
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%0 = load i32, i32* %arrayidx, align 4
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%cmp1 = icmp sgt i32 %0, 100
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br i1 %cmp1, label %if.then, label %for.inc
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if.then:
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%add = add nsw i32 %0, 20
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store i32 %add, i32* %arrayidx, align 4
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br label %for.inc
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for.inc:
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 128
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret i32 0
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}
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; Track basic blocks when unrolling conditional blocks. This code used to assert
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; because we did not update the phi nodes with the proper predecessor in the
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; vectorized loop body.
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; PR18724
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; UNROLL-NOSIMPLIFY-LABEL: bug18724
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; UNROLL-NOSIMPLIFY: store i32
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; UNROLL-NOSIMPLIFY: store i32
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define void @bug18724() {
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entry:
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br label %for.body9
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for.body9:
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br i1 undef, label %for.inc26, label %for.body14
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for.body14:
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%indvars.iv3 = phi i64 [ %indvars.iv.next4, %for.inc23 ], [ undef, %for.body9 ]
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%iNewChunks.120 = phi i32 [ %iNewChunks.2, %for.inc23 ], [ undef, %for.body9 ]
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%arrayidx16 = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 %indvars.iv3
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%tmp = load i32, i32* %arrayidx16, align 4
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br i1 undef, label %if.then18, label %for.inc23
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if.then18:
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store i32 2, i32* %arrayidx16, align 4
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%inc21 = add nsw i32 %iNewChunks.120, 1
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br label %for.inc23
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for.inc23:
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%iNewChunks.2 = phi i32 [ %inc21, %if.then18 ], [ %iNewChunks.120, %for.body14 ]
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%indvars.iv.next4 = add nsw i64 %indvars.iv3, 1
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%tmp1 = trunc i64 %indvars.iv3 to i32
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%cmp13 = icmp slt i32 %tmp1, 0
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br i1 %cmp13, label %for.body14, label %for.inc26
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for.inc26:
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%iNewChunks.1.lcssa = phi i32 [ undef, %for.body9 ], [ %iNewChunks.2, %for.inc23 ]
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unreachable
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}
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