2e5e51b3f3
This patch implements two changes:
- Move processor feature definition into a new file SystemZFeatures.td,
and provide explicit lists of supported and unsupported features for
each level of the z/Architecture. This allows specifying unsupported
features in the scheduler definition files for each processor.
- Add optional aliases for the -mcpu processor names according to the
level of the z/Architecture, for compatibility with other compilers
on the platform. The supported aliases are:
-mcpu=arch8 equals -mcpu=z10
-mcpu=arch9 equals -mcpu=z196
-mcpu=arch10 equals -mcpu=zEC12
-mcpu=arch11 equals -mcpu=z13
llvm-svn: 285577
76 lines
2.7 KiB
TableGen
76 lines
2.7 KiB
TableGen
//===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// SystemZ subtarget features
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//===----------------------------------------------------------------------===//
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include "SystemZFeatures.td"
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//===----------------------------------------------------------------------===//
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// SystemZ subtarget scheduling models
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//===----------------------------------------------------------------------===//
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include "SystemZSchedule.td"
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//===----------------------------------------------------------------------===//
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// SystemZ supported processors
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//===----------------------------------------------------------------------===//
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include "SystemZProcessors.td"
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//===----------------------------------------------------------------------===//
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// Register file description
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//===----------------------------------------------------------------------===//
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include "SystemZRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Calling convention description
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//===----------------------------------------------------------------------===//
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include "SystemZCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Instruction descriptions
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//===----------------------------------------------------------------------===//
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include "SystemZOperators.td"
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include "SystemZOperands.td"
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include "SystemZPatterns.td"
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include "SystemZInstrFormats.td"
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include "SystemZInstrInfo.td"
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include "SystemZInstrVector.td"
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include "SystemZInstrFP.td"
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def SystemZInstrInfo : InstrInfo {}
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//===----------------------------------------------------------------------===//
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// Assembly parser
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//===----------------------------------------------------------------------===//
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def SystemZAsmParser : AsmParser {
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let ShouldEmitMatchRegisterName = 0;
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}
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//===----------------------------------------------------------------------===//
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// Top-level target declaration
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//===----------------------------------------------------------------------===//
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def SystemZ : Target {
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let InstructionSet = SystemZInstrInfo;
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let AssemblyParsers = [SystemZAsmParser];
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}
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