7aad8fd8f4
This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 292982
214 lines
8.1 KiB
LLVM
214 lines
8.1 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -mattr=+fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -mattr=-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; Make sure fdiv is promoted to f32.
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; GCN-LABEL: {{^}}v_fdiv_f16
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; SI: v_cvt_f32_f16
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; SI: v_cvt_f32_f16
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; SI: v_div_scale_f32
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; SI-DAG: v_div_scale_f32
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; SI-DAG: v_rcp_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_mul_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_div_fmas_f32
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; SI: v_div_fixup_f32
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; SI: v_cvt_f16_f32
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; VI: flat_load_ushort [[LHS:v[0-9]+]]
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; VI: flat_load_ushort [[RHS:v[0-9]+]]
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; VI-DAG: v_cvt_f32_f16_e32 [[CVT_LHS:v[0-9]+]], [[LHS]]
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; VI-DAG: v_cvt_f32_f16_e32 [[CVT_RHS:v[0-9]+]], [[RHS]]
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; VI-DAG: v_rcp_f32_e32 [[RCP_RHS:v[0-9]+]], [[CVT_RHS]]
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; VI: v_mul_f32_e32 [[MUL:v[0-9]+]], [[RCP_RHS]], [[CVT_LHS]]
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; VI: v_cvt_f16_f32_e32 [[CVT_BACK:v[0-9]+]], [[MUL]]
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; VI: v_div_fixup_f16 [[RESULT:v[0-9]+]], [[CVT_BACK]], [[RHS]], [[LHS]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_fdiv_f16(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.a = getelementptr inbounds half, half addrspace(1)* %a, i64 %tid.ext
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%a.val = load volatile half, half addrspace(1)* %gep.a
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv half %a.val, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rcp_f16:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; VI-NOT: [[RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rcp_f16(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv half 1.0, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rcp_f16_abs:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e64 [[RESULT:v[0-9]+]], |[[VAL]]|
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rcp_f16_abs(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%b.abs = call half @llvm.fabs.f16(half %b.val)
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%r.val = fdiv half 1.0, %b.abs
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rcp_f16_arcp:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; VI-NOT: [[RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rcp_f16_arcp(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv arcp half 1.0, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rcp_f16_neg:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e64 [[RESULT:v[0-9]+]], -[[VAL]]
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rcp_f16_neg(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv half -1.0, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rsq_f16:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rsq_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rsq_f16(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%b.sqrt = call half @llvm.sqrt.f16(half %b.val)
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%r.val = fdiv half 1.0, %b.sqrt
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rsq_f16_neg:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_sqrt_f16_e32 [[SQRT:v[0-9]+]], [[VAL]]
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; VI-NEXT: v_rcp_f16_e64 [[RESULT:v[0-9]+]], -[[SQRT]]
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rsq_f16_neg(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%b.sqrt = call half @llvm.sqrt.f16(half %b.val)
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%r.val = fdiv half -1.0, %b.sqrt
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_fdiv_f16_arcp:
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; VI: flat_load_ushort [[LHS:v[0-9]+]]
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; VI: flat_load_ushort [[RHS:v[0-9]+]]
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; VI: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
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; VI: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[RCP]], [[LHS]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_fdiv_f16_arcp(half addrspace(1)* %r, half addrspace(1)* %a, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.a = getelementptr inbounds half, half addrspace(1)* %a, i64 %tid.ext
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%a.val = load volatile half, half addrspace(1)* %gep.a
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv arcp half %a.val, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_fdiv_f16_unsafe:
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; VI: flat_load_ushort [[LHS:v[0-9]+]]
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; VI: flat_load_ushort [[RHS:v[0-9]+]]
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; VI: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
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; VI: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[RCP]], [[LHS]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_fdiv_f16_unsafe(half addrspace(1)* %r, half addrspace(1)* %a, half addrspace(1)* %b) #2 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.a = getelementptr inbounds half, half addrspace(1)* %a, i64 %tid.ext
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%a.val = load volatile half, half addrspace(1)* %gep.a
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv half %a.val, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare half @llvm.sqrt.f16(half) #1
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declare half @llvm.fabs.f16(half) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind "unsafe-fp-math"="true" }
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